Mansour; Teymour M.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Mansour; Teymour M..The latest application filed is for "methods of resource optimization in programmable logic devices to reduce test time".
- Mansour; Teymour M. - Sunnyvale CA
| Patent | Date |
|---|---|
| Configuration and testing of multiple-die integrated circuits Grant 9,091,727 - Lupu , et al. July 28, 2 | 2015-07-28 |
| Method and apparatus for testing programmable integrated circuits Grant 8,082,535 - McEwen , et al. December 20, 2 | 2011-12-20 |
| Method and apparatus for eliminating noise induced errors during test of a programmable logic device Grant 7,558,995 - Simmons , et al. July 7, 2 | 2009-07-07 |
| Methods of resource optimization in programmable logic devices to reduce test time Grant 6,944,809 - Lai , et al. September 13, 2 | 2005-09-13 |
| Methods of resource optimization in programmable logic devices to reduce test time App 20040030975 - Lai, Andrew W. ; et al. | 2004-02-12 |
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