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name:-0.044026136398315
name:-0.024497985839844
name:-0.031153917312622
Mannebach; Ehren Patent Filings

Mannebach; Ehren

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mannebach; Ehren.The latest application filed is for "gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach".

Company Profile
26.16.45
  • Mannebach; Ehren - Beaverton OR
  • MANNEBACH; Ehren - Tigard OR
  • Mannebach; Ehren - Fond du Lac WI
  • Mannebach; Ehren - Fon du Lac WI
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Backside contacts for semiconductor devices
Grant 11,437,283 - Lilak , et al. September 6, 2
2022-09-06
Transistors stacked on front-end p-type transistors
Grant 11,437,405 - Dewey , et al. September 6, 2
2022-09-06
Self-aligned local interconnects
Grant 11,424,160 - Lilak , et al. August 23, 2
2022-08-23
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Selective Bottom-up Approach
App 20220262796 - THOMAS; Nicole ;   et al.
2022-08-18
Leave-behind Protective Layer Having Secondary Purpose
App 20220246608 - LILAK; Aaron D. ;   et al.
2022-08-04
Stacked transistor architecture including nanowire or nanoribbon thin film transistors
Grant 11,380,684 - Dewey , et al. July 5, 2
2022-07-05
Pedestal fin structure for stacked transistor integration
Grant 11,374,004 - Lilak , et al. June 28, 2
2022-06-28
Recessed metal interconnects to mitigate EPE-related via shorting
Grant 11,367,684 - Mannebach , et al. June 21, 2
2022-06-21
Stacked nanowire transistor structure with different channel geometries for stress
Grant 11,367,722 - Lilak , et al. June 21, 2
2022-06-21
Leave-behind protective layer having secondary purpose
Grant 11,348,916 - Lilak , et al. May 31, 2
2022-05-31
Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach
Grant 11,348,919 - Thomas , et al. May 31, 2
2022-05-31
Stacked transistor structures with asymmetrical terminal interconnects
Grant 11,342,227 - Lilak , et al. May 24, 2
2022-05-24
Forksheet Transistor Architectures
App 20220102346 - LILAK; Aaron D. ;   et al.
2022-03-31
Forksheet transistor architectures
Grant 11,239,236 - Lilak , et al. February 1, 2
2022-02-01
Contact Resistance Reduction In Transistor Devices With Metallization On Both Sides
App 20210408246 - GANGULY; Koustav ;   et al.
2021-12-30
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Selective Bottom-up Approach
App 20210407997 - THOMAS; Nicole ;   et al.
2021-12-30
Stacked Forksheet Transistors
App 20210407999 - HUANG; Cheng-Ying ;   et al.
2021-12-30
Stacked Transistor Structures With Asymmetrical Terminal Interconnects
App 20210305098 - Lilak; Aaron ;   et al.
2021-09-30
Forksheet Transistor Architectures
App 20210296315 - LILAK; Aaron D. ;   et al.
2021-09-23
Epitaxial Layer With Substantially Parallel Sides
App 20200411315 - HUANG; Cheng-Ying ;   et al.
2020-12-31
Device Including Air Gapping Of Gate Spacers And Other Dielectrics And Process For Providing Such
App 20200411660 - MANNEBACH; Ehren ;   et al.
2020-12-31
Memory Devices With A Logic Region Between Memory Regions
App 20200411428 - Lilak; Aaron D. ;   et al.
2020-12-31
Sideways Vias In Isolation Areas To Contact Interior Layers In Stacked Devices
App 20200411430 - MANNEBACH; Ehren ;   et al.
2020-12-31
Forming An Oxide Volume Within A Fin
App 20200411365 - HUANG; Cheng-Ying ;   et al.
2020-12-31
Stacked Source-drain-gate Connection And Process For Forming Such
App 20200411651 - MANNEBACH; Ehren ;   et al.
2020-12-31
Stacked Trigate Transistors With Dielectric Isolation And Process For Forming Such
App 20200411511 - RACHMADY; Willy ;   et al.
2020-12-31
Devices With Air Gapping Between Stacked Transistors And Process For Providing Such
App 20200411639 - MANNEBACH; Ehren ;   et al.
2020-12-31
Vertically Stacked Memory Elements With Air Gap
App 20200403033 - Lilak; Aaron D. ;   et al.
2020-12-24
Local Interconnect With Air Gap
App 20200388565 - Lin; Kevin L. ;   et al.
2020-12-10
Capacitance Reduction For Semiconductor Devices Based On Wafer Bonding
App 20200303238 - MANNEBACH; Ehren ;   et al.
2020-09-24
Stacked Transistors With Dielectric Between Source/drain Materials Of Different Strata
App 20200294969 - Rachmady; Willy ;   et al.
2020-09-17
Backside Contacts For Semiconductor Devices
App 20200294998 - LILAK; AARON D. ;   et al.
2020-09-17
Stacked Transistors With Different Crystal Orientations In Different Device Strata
App 20200295127 - Mannebach; Ehren ;   et al.
2020-09-17
Stacked Transistors Having Device Strata With Different Channel Widths
App 20200295003 - Dewey; Gilbert W. ;   et al.
2020-09-17
Stacked Transistors With Dielectric Between Channels Of Different Device Strata
App 20200266218 - Lilak; Aaron D. ;   et al.
2020-08-20
Self-aligned Local Interconnects
App 20200258778 - A1
2020-08-13
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
App 20200219979 - RACHMADY; Willy ;   et al.
2020-07-09
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approache
App 20200219970 - Mannebach; Ehren ;   et al.
2020-07-09
Self-aligned Stacked Ge/si Cmos Transistor Structure
App 20200212038 - RACHMADY; Willy ;   et al.
2020-07-02
Three Dimensional Integrated Circuits With Stacked Transistors
App 20200211905 - HUANG; Cheng-Ying ;   et al.
2020-07-02
Transistors On Heterogeneous Bonding Layers
App 20200194570 - Jun; Kimin ;   et al.
2020-06-18
Vertical Memory Cells
App 20200194435 - LILAK; Aaron ;   et al.
2020-06-18
Stacked Transistor Architecture Including Nanowire Or Nanoribbon Thin Film Transistors
App 20200105751 - Dewey; Gilbert ;   et al.
2020-04-02
Stacked Nanowire Transistor Structure With Different Channel Geometries For Stress
App 20200098756 - Lilak; Aaron ;   et al.
2020-03-26
Vertically Stacked Cmos With Upfront M0 Interconnect
App 20200098921 - RACHMADY; Willy ;   et al.
2020-03-26
Transistors Stacked On Front-end P-type Transistors
App 20200006388 - DEWEY; Gilbert ;   et al.
2020-01-02
Leave-behind Protective Layer Having Secondary Purpose
App 20200006330 - LILAK; AARON D. ;   et al.
2020-01-02
Interconnect Techniques For Electrically Connecting Source/drain Regions Of Stacked Transistors
App 20200006329 - LILAK; AARON D. ;   et al.
2020-01-02
Techniques For Forming Gate Structures For Transistors Arranged In A Stacked Configuration On A Single Fin Structure
App 20200006331 - LILAK; AARON D. ;   et al.
2020-01-02
Pedestal Fin Structure For Stacked Transistor Integration
App 20200006340 - LILAK; AARON D. ;   et al.
2020-01-02
Recessed Metal Interconnects To Mitigate Epe-related Via Shorting
App 20190355665 - MANNEBACH; Ehren ;   et al.
2019-11-21
Stacked Transistors With Different Gate Lengths In Different Device Strata
App 20190196830 - Lilak; Aaron D. ;   et al.
2019-06-27
Analogue ionic liquids for the separation and recovery of hydrocarbons from particulate matter
Grant 9,447,329 - Painter , et al. September 20, 2
2016-09-20
Analogue Ionic Liquids For The Separation And Recovery Of Hydrocarbons From Particulate Matter
App 20140054200 - PAINTER; Paul ;   et al.
2014-02-27
Analogue ionic liquids for the separation and recovery of hydrocarbons from particulate matter
Grant 8,603,327 - Painter , et al. December 10, 2
2013-12-10
Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter
Grant 8,603,326 - Painter , et al. December 10, 2
2013-12-10
Analogue Ionic Liquids For The Separation And Recovery Of Hydrocarbons From Particulate Matter
App 20120048783 - Painter; Paul ;   et al.
2012-03-01
Systems, Methods And Compositions For The Separation And Recovery Of Hydrocarbons From Particulate Matter
App 20110042318 - Painter; Paul ;   et al.
2011-02-24

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