Mann; Randy W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mann; Randy W..The latest application filed is for "sram bit cells formed with dummy structures".

Company Profile

11.75.62

Mann; Randy W. - Milton NY
Mann; Randy W. - Poughquag NY US
Mann; Randy W. - Burlington NC
Mann; Randy W. - Williston VT
Mann; Randy W. - Jerhico VT
Mann; Randy W. - Jericho VT
Mann, Randy W - Poughquag NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structures and SRAM bit cells integrating complementary field-effect transistors Grant 11,309,319 - Mann , et al. April 19, 2	2022-04-19
SRAM bit cells formed with dummy structures Grant 11,037,937 - Zhao , et al. June 15, 2	2021-06-15
Sram Bit Cells Formed With Dummy Structures App 20210151443 - Zhao; Meixiong ; et al.	2021-05-20
Structures And Sram Bit Cells Integrating Complementary Field-effect Transistors App 20200365601 - Mann; Randy W. ; et al.	2020-11-19
Structures and SRAM bit cells integrating complementary field-effect transistors Grant 10,818,674 - Mann , et al. October 27, 2	2020-10-27
Structures And Sram Bit Cells Integrating Complementary Field-effect Transistors App 20200286900 - Mann; Randy W. ; et al.	2020-09-10
Static random access memory cells with arranged vertical-transport field-effect transistors Grant 10,629,602 - Mann , et al.	2020-04-21
SRAM structure with alternate gate pitches Grant 10,497,692 - Zang , et al. De	2019-12-03
Static Random Access Memory Cells With Arranged Vertical-transport Field-effect Transistors App 20190355730 - Mann; Randy W. ; et al.	2019-11-21
Dual port vertical transistor memory cell Grant 10,439,064 - Mann , et al. O	2019-10-08
Six-transistor (6T) SRAM cell structure Grant 10,403,629 - Mann , et al. Sep	2019-09-03
Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails Grant 10,332,897 - Zhang , et al.	2019-06-25
Novel Six-transistor (6t) Sram Cell Structure App 20190139967 - Mann; Randy W. ; et al.	2019-05-09
Sram Structure With Alternate Gate Pitches App 20190067262 - ZANG; Hui ; et al.	2019-02-28
Method Of Reducing Fin Width In Finfet Sram Array To Mitigate Low Voltage Strap Bit Fails App 20190019798 - Zhang; Xiaoqiang ; et al.	2019-01-17
Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails Grant 10,163,914 - Zhang , et al. Dec	2018-12-25
Cross couple structure for vertical transistors Grant 10,109,637 - Zang , et al. October 23, 2	2018-10-23
Method Of Reducing Fin Width In Finfet Sram Array To Mitigate Low Voltage Strap Bit Fails App 20180261605 - Zhang; Xiaoqiang ; et al.	2018-09-13
Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method Grant 10,068,902 - Shen , et al. September 4, 2	2018-09-04
Methods, apparatus, and system for global healing of write-limited die through bias temperature instability Grant 10,068,660 - Gautam , et al. September 4, 2	2018-09-04
Method, apparatus, and system for targeted healing of write fails through bias temperature instability Grant 9,916,212 - Gautam , et al. March 13, 2	2018-03-13
Methods, Apparatus, And System For Global Healing Of Write-limited Die Through Bias Temperature Instability App 20170271032 - Gautam; Akhilesh ; et al.	2017-09-21
Method, Apparatus, And System For Targeted Healing Of Write Fails Through Bias Temperature Instability App 20170242759 - Gautam; Akhilesh ; et al.	2017-08-24
Method, apparatus, and system for global healing of write-limited die through bias temperature instability Grant 9,704,600 - Gautam , et al. July 11, 2	2017-07-11
Method, apparatus, and system for global healing of stability-limited die through bias temperature instability Grant 9,601,187 - Gautam , et al. March 21, 2	2017-03-21
Method, apparatus and system for targeted healing of stability failures through bias temperature instability Grant 9,601,188 - Gautam , et al. March 21, 2	2017-03-21
Methods, apparatus and system determining dual port DC contention margin Grant 9,530,488 - Balasubramanian , et al. December 27, 2	2016-12-27
Wafer test structures and methods of providing wafer test structures Grant 9,372,226 - Uppal , et al. June 21, 2	2016-06-21
Memory cell Grant 9,337,204 - Calhoun , et al. May 10, 2	2016-05-10
Wafer Test Structures And Methods Of Providing Wafer Test Structures App 20160025805 - UPPAL; Suresh ; et al.	2016-01-28
Integrated circuit with semiconductor fin fuse Grant 9,219,040 - Mann , et al. December 22, 2	2015-12-22
Dual port SRAM bitcell structures with improved transistor arrangement Grant 9,202,552 - Paul , et al. December 1, 2	2015-12-01
Modeling memory cell skew sensitivity Grant 9,069,922 - Paul , et al. June 30, 2	2015-06-30
Dual Port Sram Bitcell Structures With Improved Transistor Arrangement App 20150170735 - PAUL; Bipul C. ; et al.	2015-06-18
SRAM cell with individual electrical device threshold control Grant 9,048,136 - Mann , et al. June 2, 2	2015-06-02
Memory Cell App 20150147857 - Calhoun; Benton H. ; et al.	2015-05-28
SRAM cell with individual electrical device threshold control Grant 9,029,956 - Mann , et al. May 12, 2	2015-05-12
Memory cell including unidirectional gate conductors and contacts Grant 8,947,912 - Calhoun , et al. February 3, 2	2015-02-03
Integrated circuit with stress generator for stressing test devices Grant 8,907,687 - McMahon , et al. December 9, 2	2014-12-09
Integrated Circuit With A Fin-based Fuse, And Related Fabrication Method App 20140021579 - Mann; Randy W. ; et al.	2014-01-23
Memory Cell With Asymmetric Read Port Transistors App 20130341723 - Mojumder; Niladri N. ; et al.	2013-12-26
Modeling Memory Cell Skew Sensitivity App 20130332136 - Paul; Bipul C. ; et al.	2013-12-12
Semiconductor device and method of fabrication Grant 8,597,994 - Mann December 3, 2	2013-12-03
Integrated Circuit With Stress Generator For Stressing Test Devices App 20130293250 - McMahon; William ; et al.	2013-11-07
Integrated circuit with a fin-based fuse, and related fabrication method Grant 8,569,116 - Mann , et al. October 29, 2	2013-10-29
Electrically conductive path forming below barrier oxide layer and integrated circuit Grant 8,563,398 - Costrini , et al. October 22, 2	2013-10-22
Memory Cell App 20130242645 - Calhoun; Benton H. ; et al.	2013-09-19
Sram Cell With Individual Electrical Device Threshold Control App 20130107608 - Mann; Randy W. ; et al.	2013-05-02
Sram Cell With Individual Electrical Device Threshold Control App 20130107610 - Mann; Randy W. ; et al.	2013-05-02
Semiconductor Device And Method Of Fabrication App 20120299106 - MANN; Randy W.	2012-11-29
Circuit design Grant 8,099,688 - Ellis , et al. January 17, 2	2012-01-17
Highly tunable metal-on-semiconductor trench varactor Grant 7,989,922 - Mann , et al. August 2, 2	2011-08-02
Electrically Conductive Path Forming Below Barrier Oxide Layer And Integrated Circuit App 20110092056 - Costrini; Gregory ; et al.	2011-04-21
Electrically conductive path forming below barrier oxide layer and integrated circuit Grant 7,923,840 - Costrini , et al. April 12, 2	2011-04-12
Methods of base formation in a BiCOMS process Grant 7,696,034 - Geiss , et al. April 13, 2	2010-04-13
Highly Tunable Metal-on-semiconductor Trench Varactor App 20090200642 - Mann; Randy W. ; et al.	2009-08-13
Structure for SRAM voltage control for improved operational margins App 20090129191 - Ellis; Wayne F. ; et al.	2009-05-21
SRAM voltage control for improved operational margins Grant 7,466,604 - Ellis , et al. December 16, 2	2008-12-16
METHODS OF BASE FORMATION IN A BiCMOS PROCESS App 20080268604 - Geiss; Peter J. ; et al.	2008-10-30
Electrically Conductive Path Forming Below Barrier Oxide Layer And Integrated Circuit App 20080166857 - Costrini; Gregory ; et al.	2008-07-10
Methods of base formation in a BiCMOS process Grant 7,390,721 - Geiss , et al. June 24, 2	2008-06-24
SRAM voltage control for improved operational margins App 20080089116 - Ellis; Wayne F. ; et al.	2008-04-17
SRAM voltage control for improved operational margins Grant 7,313,032 - Ellis , et al. December 25, 2	2007-12-25
Isolated Fully Depleted Silicon-on-insulator Regions By Selective Etch App 20070128776 - Breitwisch; Matthew J. ; et al.	2007-06-07
Sram Voltage Control For Improved Operational Margins App 20070121370 - Ellis; Wayne F. ; et al.	2007-05-31
Low-cost deep trench decoupling capacitor device and process of manufacture Grant 7,193,262 - Ho , et al. March 20, 2	2007-03-20
Isolated fully depleted silicon-on-insulator regions by selective etch Grant 7,190,007 - Breitwisch , et al. March 13, 2	2007-03-13
Structure and method for local resistor element in integrated circuit technology Grant 7,166,904 - Gill , et al. January 23, 2	2007-01-23
Method for scalable, low-cost polysilicon capacitor in a planar DRAM Grant 7,087,486 - Brown , et al. August 8, 2	2006-08-08
FinFET SRAM cell using low mobility plane for cell stability and method for forming Grant 7,087,477 - Fried , et al. August 8, 2	2006-08-08
Grounded body SOI SRAM cell Grant 7,075,153 - Assaderaghi , et al. July 11, 2	2006-07-11
Low-Cost Deep Trench Decoupling Capacitor Device and Process of Manufacture App 20060124982 - Ho; Herbert L. ; et al.	2006-06-15
Detector for alpha particle or cosmic ray Grant 7,057,180 - Fifield , et al. June 6, 2	2006-06-06
Zero threshold voltage pFET and method of making same Grant 7,005,334 - Brown , et al. February 28, 2	2006-02-28
Isolated fully depleted silicon-on-insulator regions by selective etch App 20060027889 - Breitwisch; Matthew J. ; et al.	2006-02-09
Methods of base formation in a BiCMOS process App 20060017066 - Geiss; Peter J. ; et al.	2006-01-26
Finfet SRAM cell using low mobility plane for cell stability and method for forming Grant 6,967,351 - Fried , et al. November 22, 2	2005-11-22
Method of base formation in a BiCMOS process Grant 6,965,133 - Geiss , et al. November 15, 2	2005-11-15
High mobility transistors in SOI and method for forming Grant 6,962,838 - Anderson , et al. November 8, 2	2005-11-08
Symmetric device with contacts self aligned to gate Grant 6,946,376 - Chediak , et al. September 20, 2	2005-09-20
Method Of Base Formation In A Bicmos Process App 20050199908 - Geiss, Peter J. ; et al.	2005-09-15
Structure And Method For Local Resistor Element In Integrated Circuit Technology App 20050167786 - Gill, Jason P. ; et al.	2005-08-04
Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits Grant 6,917,221 - Bernstein , et al. July 12, 2	2005-07-12
Method for scalable, low-cost polysilicon capacitor in a planar dram App 20050148140 - Brown, Jeffrey S. ; et al.	2005-07-07
FinFET SRAM cell using low mobility plane for cell stability and method for forming App 20050121676 - Fried, David M. ; et al.	2005-06-09
Method of forming refractory metal contact in an opening, and resulting structure Grant 6,900,505 - Chapple-Sokol , et al. May 31, 2	2005-05-31
Methods and apparatus for employing feedback body control in cross-coupled inverters Grant 6,891,419 - Kartschoke , et al. May 10, 2	2005-05-10
Selective silicide blocking Grant 6,881,672 - Breitwisch , et al. April 19, 2	2005-04-19
Methods And Apparatus For Employing Feedback Body Control In Cross-coupled Inverters App 20050024113 - Kartschoke, Paul D. ; et al.	2005-02-03
Detector For Alpha Particle Or Cosmic Ray App 20050012045 - Fifield, John A. ; et al.	2005-01-20
Zero Threshold Voltage Pfet And Method Of Making Same App 20040251496 - Brown, Jeffrey S. ; et al.	2004-12-16
Zero threshold voltage pFET and method of making same App 20040251475 - Brown, Jeffrey S. ; et al.	2004-12-16
Zero Threshold Voltage pFET and method of making same Grant 6,825,530 - Brown , et al. November 30, 2	2004-11-30
Structure for scalable, low-cost polysilicon DRAM in a planar capacitor Grant 6,815,751 - Brown , et al. November 9, 2	2004-11-09
Method And Apparatus For Enhancing The Soft Error Rate Immunity Of Dynamic Logic Circuits App 20040216015 - Bernstein, Kerry ; et al.	2004-10-28
Method and design for measuring SRAM array leakage macro (ALM) Grant 6,778,449 - Breitwisch , et al. August 17, 2	2004-08-17
Method of forming refractory metal contact in an opening, and resulting structure Grant 6,762,121 - Chapple-Sokol , et al. July 13, 2	2004-07-13
Selective silicide blocking App 20040110371 - Breitwisch, Matthew J. ; et al.	2004-06-10
Grounded body SOI SRAM cell App 20040048425 - Assaderaghi, Fariborz ; et al.	2004-03-11
Selective silicide blocking Grant 6,700,163 - Breitwisch , et al. March 2, 2	2004-03-02
Structure For Scalable, Low-cost Polysilicon Dram In A Planar Capaacitor App 20040000685 - Brown, Jeffrey S. ; et al.	2004-01-01
Method and design for measuring SRAM array leakage macro (ALM) App 20040001376 - Breitwisch, Matthew J. ; et al.	2004-01-01
High mobility transistors in SOI and method for forming App 20030232467 - Anderson, Brent A. ; et al.	2003-12-18
Grounded body SOI SRAM cell Grant 6,646,305 - Assaderaghi , et al. November 11, 2	2003-11-11
High mobility transistors in SOI and method for forming Grant 6,624,478 - Anderson , et al. September 23, 2	2003-09-23
SOI low capacitance body contact Grant 6,624,475 - Bryant , et al. September 23, 2	2003-09-23
Method of forming refractory metal contact in an opening, and resulting structure App 20030165705 - Chapple-Sokol, Jonathan D. ; et al.	2003-09-04
High Mobility Transistors In Soi And Method For Forming App 20030141548 - Anderson, Brent A. ; et al.	2003-07-31
Selective silicide blocking App 20030107091 - Breitwisch, Matthew J. ; et al.	2003-06-12
Finfet SRAM cell using low mobility plane for cell stability and method for forming App 20030102518 - Fried, David M. ; et al.	2003-06-05
Grounded body SOI SRAM cell App 20030020116 - Assaderaghi, Fariborz ; et al.	2003-01-30
Semiconductor structure having heterogenous silicide regions having titanium and molybdenum Grant 6,512,296 - Gauthier, Jr. , et al. January 28, 2	2003-01-28
Angled implant process Grant 6,489,223 - Hook , et al. December 3, 2	2002-12-03
Symmetric device with contacts self aligned to gate App 20020158286 - Chediak, Juan A. ; et al.	2002-10-31
MOSFET with lateral resistor ballasting Grant 6,441,410 - Gauthier, Jr. , et al. August 27, 2	2002-08-27
SOI low capacitance body contact App 20020053702 - Bryant, Andres ; et al.	2002-05-09
Nvram Cell With Planar Control Gate App 20020003254 - MOLINELLI ACOCELLA, JOYCE E. ; et al.	2002-01-10
Method Of Forming Resist Images By Periodic Pattern Removal App 20010041306 - COLE, DANIEL C. ; et al.	2001-11-15
MOSFET with lateral resistor ballasting App 20010031552 - Gauthier, Robert J. JR. ; et al.	2001-10-18
Semiconductor structure having heterogeneous silicide regions and method for forming same Grant 6,187,617 - Gauthier, Jr. , et al. February 13, 2	2001-02-13
Method for lowering the phase transformation temperature of a metal silicide Grant 5,510,295 - Cabral, Jr. , et al. April 23, 1	1996-04-23
Method of making overpass mask/insulator for local interconnects Grant 5,496,771 - Cronin , et al. March 5, 1	1996-03-05
Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits Grant 5,453,400 - Abernathey , et al. September 26, 1	1995-09-26