Mandava; Sreenivas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mandava; Sreenivas.The latest application filed is for "memory transaction queue bypass based on configurable address and bandwidth conditions".

Company Profile

3.8.18

Mandava; Sreenivas - Los Altos CA
MANDAVA; Sreenivas - Los Atlos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory Transaction Queue Bypass Based On Configurable Address And Bandwidth Conditions App 20220179797 - Swanson; Jeffrey C. ; et al.	2022-06-09
Address Generation For Adaptive Double Device Data Correction Sparing App 20220108764 - LING; Jing ; et al.	2022-04-07
Detection Of Data Corruption In Memory Address Decode Circuitry App 20220091764 - MANDAVA; Sreenivas ; et al.	2022-03-24
Data Scrambler To Mitigate Row Hammer Corruption App 20210382638 - ANDERSON; Ronald ; et al.	2021-12-09
Deferred Ecc (error Checking And Correction) Memory Initialization By Memory Scrub Hardware App 20210382640 - MANDAVA; Sreenivas ; et al.	2021-12-09
Method And Apparatus For Memory Chip Row Hammer Threat Backpressure Signal And Host Side Response App 20210264999 - BAINS; Kuljit S. ; et al.	2021-08-26
Temperature-based Runtime Variability In Victim Address Selection For Probabilistic Schemes For Row Hammer App 20210109577 - MANDAVA; Sreenivas ; et al.	2021-04-15
Fast boot up memory controller Grant 10,552,643 - Lovelace , et al. Fe	2020-02-04
Apparatus and method for system physical address to memory module address translation Grant 10,162,761 - Raj , et al. Dec	2018-12-25
Techniques for probabilistic dynamic random access memory row repair Grant 10,102,886 - Crawford , et al. October 16, 2	2018-10-16
Apparatus And Method For System Physical Address To Memory Module Address Translation App 20180276137 - RAJ; ASHOK ; et al.	2018-09-27
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device Grant 10,042,562 - Geetha , et al. August 7, 2	2018-08-07
Fast Boot Up Memory Controller App 20180181336 - LOVELACE; John V. ; et al.	2018-06-28
Apparatus And Method For A Non-power-of-2 Size Cache In A First Level Memory Device To Cache Data Present In A Second Level Memory Device App 20180004433 - GEETHA; Vedaraman ; et al.	2018-01-04
Techniques for determining victim row addresses in a volatile memory Grant 9,824,754 - Mandava , et al. November 21, 2	2017-11-21
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device Grant 9,747,041 - Geetha , et al. August 29, 2	2017-08-29
Apparatus And Method For A Non-power-of-2 Size Cache In A First Level Memory Device To Cache Data Present In A Second Level Memory Device App 20170185315 - Geetha; Vedaraman ; et al.	2017-06-29
Techniques for Probabilistic Dynamic Random Access Memory Row Repair App 20170103795 - Crawford; John H. ; et al.	2017-04-13
Techniques for probabilistic dynamic random access memory row repair Grant 9,449,671 - Crawford , et al. September 20, 2	2016-09-20
Techniques for Determining Victim Row Addresses in a Volatile Memory App 20160224262 - MANDAVA; SREENIVAS ; et al.	2016-08-04
Techniques for determining victim row addresses in a volatile memory Grant 9,269,436 - Mandava , et al. February 23, 2	2016-02-23
Techniques for Determining Victim Row Addresses in a Volatile Memory App 20140281207 - Mandava; Sreenivas ; et al.	2014-09-18
Techniques for Probabilistic Dynamic Random Access Memory Row Repair App 20140281206 - Crawford; John H. ; et al.	2014-09-18

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