| Patent | Date |
|---|
Apparatus and method of application virtualization
App 20070168937 - Mallick; Soummya | 2007-07-19 |
Expandable portable solid-state device & method
App 20070094439 - Kumar; Santosh ; et al. | 2007-04-26 |
Apparatus and method of an executable-in-place flash device
App 20060294356 - Kumar; Santosh ; et al. | 2006-12-28 |
Data path media security system and method in a storage area network
App 20050080761 - Sundararajan, Kumar ; et al. | 2005-04-14 |
Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
Grant 6,212,542 - Kahle , et al. April 3, 2 | 2001-04-03 |
Apparatus and method for reducing the number of rename registers required in the operation of a processor
Grant 6,061,777 - Cheong , et al. May 9, 2 | 2000-05-09 |
Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution
Grant 5,961,639 - Mallick , et al. October 5, 1 | 1999-10-05 |
Address translation buffer for data processing system emulation mode
Grant 5,953,520 - Mallick September 14, 1 | 1999-09-14 |
Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
Grant 5,913,925 - Kahle , et al. June 22, 1 | 1999-06-22 |
Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle
Grant 5,913,054 - Mallick , et al. June 15, 1 | 1999-06-15 |
System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference
Grant 5,897,655 - Mallick April 27, 1 | 1999-04-27 |
Generation of unique address alias for memory disambiguation buffer to avoid false collisions
Grant 5,897,666 - Mallick , et al. April 27, 1 | 1999-04-27 |
Method and system for constructing a program including a navigation instruction
Grant 5,887,166 - Mallick , et al. March 23, 1 | 1999-03-23 |
Processor and method for out-of-order execution of instructions based upon an instruction parameter
Grant 5,872,948 - Mallick , et al. February 16, 1 | 1999-02-16 |
System and method for reducing power consumption in an electronic circuit
Grant 5,870,616 - Loper , et al. February 9, 1 | 1999-02-09 |
Indirect unconditional branches in data processing system emulation mode
Grant 5,870,575 - Kahle , et al. February 9, 1 | 1999-02-09 |
Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction
Grant 5,867,684 - Kahle , et al. February 2, 1 | 1999-02-02 |
Method and system for performing an emulation context save and restore that is transparent to the operating system
Grant 5,812,823 - Kahle , et al. September 22, 1 | 1998-09-22 |
Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue
Grant 5,812,812 - Afsar , et al. September 22, 1 | 1998-09-22 |
Method and apparatus for dynamic allocation of registers for intermediate floating-point results
Grant 5,805,916 - Mallick , et al. September 8, 1 | 1998-09-08 |
System and method for reducing power consumption in an electronic circuit
Grant 5,805,907 - Loper , et al. September 8, 1 | 1998-09-08 |
Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache
Grant 5,802,572 - Patel , et al. September 1, 1 | 1998-09-01 |
Method and system of executing speculative store instructions in a parallel processing computer system
Grant 5,802,340 - Mallick , et al. September 1, 1 | 1998-09-01 |
Latency-based scheduling of instructions in a superscalar processor
Grant 5,802,386 - Kahle , et al. September 1, 1 | 1998-09-01 |
Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation
Grant 5,787,479 - Jessani , et al. July 28, 1 | 1998-07-28 |
Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization
Grant 5,764,969 - Kahle , et al. June 9, 1 | 1998-06-09 |
Method and system for efficient rename buffer deallocation within a processor
Grant 5,765,215 - Afsar , et al. June 9, 1 | 1998-06-09 |
Method and system for emulating instructions by performing an operation directly using special-purpose register contents
Grant 5,758,140 - Kahle , et al. May 26, 1 | 1998-05-26 |
Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor
Grant 5,758,117 - Patel , et al. May 26, 1 | 1998-05-26 |
Instruction dispatch queue for improved instruction cache to queue timing
Grant 5,754,811 - Putrino , et al. May 19, 1 | 1998-05-19 |
Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
Grant 5,752,014 - Mallick , et al. May 12, 1 | 1998-05-12 |
Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions
Grant 5,694,565 - Kahle , et al. December 2, 1 | 1997-12-02 |
Method and system for recoding noneffective instructions within a data processing system
Grant 5,619,408 - Black , et al. April 8, 1 | 1997-04-08 |
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