Malik; Sharad

Patent Applications and Registrations

Patent applications and USPTO patent grants for Malik; Sharad.The latest application filed is for "method for design validation using retiming".

Company Profile

0.15.5

Malik; Sharad - Princeton NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for efficient implementation of boolean satisfiability Grant 7,418,369 - Moskewicz , et al. August 26, 2	2008-08-26
Placement method for integrated circuit design using topo-clustering Grant 6,961,916 - Sarrafzadeh , et al. November 1, 2	2005-11-01
Method for design validation using retiming App 20050149301 - Gupta, Aarti ; et al.	2005-07-07
Method for design validation using retiming Grant 6,874,135 - Gupta , et al. March 29, 2	2005-03-29
Partition-based decision heuristics for SAT and image computation using SAT and BDDs Grant 6,651,234 - Gupta , et al. November 18, 2	2003-11-18
Method For Design Validation Using Retiming App 20030182638 - GUPTA, AARTI ; et al.	2003-09-25
Method and system for efficient implementation of boolean satisfiability App 20030084411 - Moskewicz, Matthew ; et al.	2003-05-01
Partition-based decision heuristics for SAT and image computation using SAT and BDDs App 20020178424 - Gupta, Aarti ; et al.	2002-11-28
Placement method for integrated circuit design using topo-clustering App 20020138816 - Sarrafzadeh, Majid ; et al.	2002-09-26
Placement method for integrated circuit design using topo-clustering Grant 6,442,743 - Sarrafzadeh , et al. August 27, 2	2002-08-27
System and method for concurrent buffer insertion and placement of logic gates Grant 6,367,051 - Pileggi , et al. April 2, 2	2002-04-02
Method for design optimization using logical and physical information Grant 6,286,128 - Pileggi , et al. September 4, 2	2001-09-04
Configurable hardware system implementing Boolean Satisfiability and method thereof Grant 6,247,164 - Ashar , et al. June 12, 2	2001-06-12
Method for logic optimization for improving timing and congestion during placement in integrated circuit design Grant 6,192,508 - Malik , et al. February 20, 2	2001-02-20
Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware Grant 6,038,392 - Ashar , et al. March 14, 2	2000-03-14
Method for using complete-1-distinguishability for FSM equivalence checking Grant 6,035,109 - Ashar , et al. March 7, 2	2000-03-07
Enhanced binary decision diagram-based functional simulation Grant 5,937,183 - Ashar , et al. August 10, 1	1999-08-10
System and method for processing graphic delay data of logic circuit to reduce topological redundancy Grant 5,841,673 - Kobayashi , et al. November 24, 1	1998-11-24
Method of finding minimum-cost feedback-vertex sets for a graph for partial scan testing without exhaustive cycle enumeration Grant 5,522,063 - Ashar , et al. May 28, 1	1996-05-28
Timing analysis of VLSI circuits Grant 5,457,638 - Ashar , et al. October 10, 1	1995-10-10

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