Mal Jain; Paras
Patent Applications and Registrations
Patent applications and USPTO patent grants for Mal Jain; Paras.The latest application filed is for "verifying glitches in reset path using formal verification and simulation".
- Mal Jain; Paras - Cupertino CA
- Mal Jain; Paras - Greater Noida IN
- Mal Jain; Paras - Alwar IN
- Mal Jain; Paras - San Jose CA
| Patent | Date |
|---|---|
| Verifying glitches in reset path using formal verification and simulation Grant 11,238,202 - Mondal , et al. February 1, 2 | 2022-02-01 |
| Verifying Glitches In Reset Path Using Formal Verification And Simulation App 20200401750 - MONDAL; Sudeep ; et al. | 2020-12-24 |
| System and method for netlist clock domain crossing verification Grant 9,721,057 - Ganai , et al. August 1, 2 | 2017-08-01 |
| Method And System For Checking And Correcting Shoot-through In Rtl Simulation App 20160342727 - Sarwary; Mohamed Shaker ; et al. | 2016-11-24 |
| System And Method For Netlist Clock Domain Crossing Verification App 20160259879 - Ganai; Malay ; et al. | 2016-09-08 |
| Method for recognizing and verifying FIFO structures in integrated circuit designs Grant 7,536,662 - Sarwary , et al. May 19, 2 | 2009-05-19 |
| A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design App 20060190754 - Dargelas; Alain ; et al. | 2006-08-24 |
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