Maki; Andrew Benson

Patent Applications and Registrations

Patent applications and USPTO patent grants for Maki; Andrew Benson.The latest application filed is for "clock frequency adjustment for workload changes in integrated circuit devices".

Company Profile

1.40.40

Maki; Andrew Benson - Woodinville WA
Maki; Andrew Benson - Rochester MN US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Clock frequency adjustment for workload changes in integrated circuit devices Grant 11,209,886 - Hovis , et al. December 28, 2	2021-12-28
Clock Frequency Adjustment For Workload Changes In Integrated Circuit Devices App 20210081016 - Hovis; William Paul ; et al.	2021-03-18
Method and apparatus for measurement and control of photomask to substrate alignment Grant 8,535,393 - Granados , et al. September 17, 2	2013-09-17
Method and apparatus for measurement and control of photomask to substrate alignment Grant 8,536,587 - Granados , et al. September 17, 2	2013-09-17
Implementing selective rework for chip stacks and silicon carrier assemblies Grant 8,519,304 - Bartley , et al. August 27, 2	2013-08-27
Enhanced architectural interconnect options enabled with flipped die on a multi-chip package Grant 8,174,103 - Bartley , et al. May 8, 2	2012-05-08
Enhanced conductivity in an airgapped integrated circuit Grant 8,108,820 - Aguado Granados , et al. January 31, 2	2012-01-31
Implementing Selective Rework For Chip Stacks And Silicon Carrier Assemblies App 20120006803 - Bartley; Gerald Keith ; et al.	2012-01-12
Method of enhancing on-chip inductance structure utilizing silicon through via technology Grant 8,079,134 - Maki , et al. December 20, 2	2011-12-20
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110269077 - Granados; Axel Aguado ; et al.	2011-11-03
Implementing vertical airgap structures between chip metal layers Grant 7,989,337 - Aguado Granados , et al. August 2, 2	2011-08-02
Cost-benefit optimization for an airgapped integrated circuit Grant 7,979,824 - Aguado Granados , et al. July 12, 2	2011-07-12
Implementing enhanced wiring capability for electronic laminate packages Grant 7,954,081 - Bartley , et al. May 31, 2	2011-05-31
Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design Grant 7,945,883 - Bartley , et al. May 17, 2	2011-05-17
Method and apparatus for measurement and control of photomask to substrate alignment Grant 7,935,546 - Granados , et al. May 3, 2	2011-05-03
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110096329 - Granados; Axel Aguado ; et al.	2011-04-28
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110096310 - Granados; Axel Aguado ; et al.	2011-04-28
Method and apparatus for measurement and control of photomask to substrate alignment Grant 7,875,987 - Granados , et al. January 25, 2	2011-01-25
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110013187 - Granados; Axel Aguado ; et al.	2011-01-20
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110008719 - Granados; Axel Aguado ; et al.	2011-01-13
Implementing at-speed Wafer Final Test (WFT) with complete chip coverage Grant 7,852,103 - Bartley , et al. December 14, 2	2010-12-14
Computer system having an apportionable data bus and daisy chained memory chips Grant 7,844,769 - Bartley , et al. November 30, 2	2010-11-30
Implementing Vertical Airgap Structures Between Chip Metal Layers App 20100270682 - Aguado Granados; Axel ; et al.	2010-10-28
Implementing At-speed Wafer Final Test (wft) With Complete Chip Coverage App 20100271046 - Bartley; Gerald Keith ; et al.	2010-10-28
Cost-Benefit Optimization for an Airgapped Integrated Circuit App 20100064270 - Aguado Granados; Axel ; et al.	2010-03-11
Enhanced Conductivity in an Airgapped Integrated Circuit App 20100063781 - Aguado Granados; Axel ; et al.	2010-03-11
Method and structure for connecting, stacking, and cooling chips on a flexible carrier Grant 7,675,164 - Bartley , et al. March 9, 2	2010-03-09
Computer system having daisy chained memory chips Grant 7,673,093 - Bartley , et al. March 2, 2	2010-03-02
Daisy chainable self timed memory chip Grant 7,660,942 - Bartley , et al. February 9, 2	2010-02-09
Carrier having daisy chain of self timed memory chips Grant 7,660,940 - Bartley , et al. February 9, 2	2010-02-09
Enhanced On-Chip Inductance Structure Utilizing Silicon Through Via Technology App 20100024202 - Maki; Andrew Benson ; et al.	2010-02-04
Memory controller for daisy chained memory chips Grant 7,627,711 - Bartley , et al. December 1, 2	2009-12-01
Memory chip having an apportionable data bus Grant 7,620,763 - Bartley , et al. November 17, 2	2009-11-17
Carrier having daisy chained memory chips Grant 7,617,350 - Bartley , et al. November 10, 2	2009-11-10
Enhanced Architectural Interconnect Options Enabled With Flipped Die on a Multi-Chip Package App 20090273098 - Bartley; Gerald Keith ; et al.	2009-11-05
Memory controller for daisy chained self timed memory chips Grant 7,577,811 - Bartley , et al. August 18, 2	2009-08-18
Method and Apparatus for Measurement and Control of Photomask to Substrate Alignment App 20090195787 - Granados; Axel Aguado ; et al.	2009-08-06
Method for implementing component placement suspended within grid array packages for enhanced electrical performance Grant 7,553,696 - Bartley , et al. June 30, 2	2009-06-30
Self timed memory chip having an apportionable data bus Grant 7,546,410 - Bartley , et al. June 9, 2	2009-06-09
Memory system having self timed daisy chained memory chips Grant 7,545,664 - Bartley , et al. June 9, 2	2009-06-09
Implementing Enhanced Wiring Capability For Electronic Laminate Packages App 20090138832 - Bartley; Gerald Keith ; et al.	2009-05-28
Enhanced CML driver circuit for "quiet-driver" measurement enablement Grant 7,532,037 - Granados , et al. May 12, 2	2009-05-12
Method and Apparatus for Measurement and Control of Photomask to Substrate Alignment App 20090081813 - Aguado Granados; Axel ; et al.	2009-03-26
Memory system having an apportionable data bus and daisy chained memory chips Grant 7,490,186 - Bartley , et al. February 10, 2	2009-02-10
Daisy chainable memory chip Grant 7,480,201 - Bartley , et al. January 20, 2	2009-01-20
Method for implementing enhanced wiring capability for electronic laminate packages Grant 7,472,360 - Bartley , et al. December 30, 2	2008-12-30
Method for implementing vertically coupled noise control through a mesh plane in an electronic package design Grant 7,472,368 - Bartley , et al. December 30, 2	2008-12-30
Apparatus, And Computer Program Product For Implementing Vertically Coupled Noise Control Through A Mesh Plane In An Electronic Package Design App 20080270968 - Bartley; Gerald Keith ; et al.	2008-10-30
Method and Structure for Connecting, Stacking, and Cooling Chips on a Flexible Carrier App 20080218974 - Bartley; Gerald Keith ; et al.	2008-09-11
Power Control Structure For Managing A Plurality Of Voltage Islands App 20080185734 - Bartley; Gerald Keith ; et al.	2008-08-07
Method, Apparatus, and Computer Program Product for Implementing Balanced Wiring Delay Within an Electronic Package App 20080178136 - Bartley; Gerald Keith ; et al.	2008-07-24
Method and power control structure for managing plurality of voltage islands Grant 7,402,912 - Bartley , et al. July 22, 2	2008-07-22
Daisy chained memory system Grant 7,345,900 - Bartley , et al. March 18, 2	2008-03-18
Computer system having daisy chained self timed memory chips Grant 7,345,901 - Bartley , et al. March 18, 2	2008-03-18
Daisy chainable memory chip Grant 7,342,816 - Bartley , et al. March 11, 2	2008-03-11
Method and Structure for Implementing Component Placement Suspended within Grid Array Packages for Enhanced Electrical Performance App 20080054453 - Bartley; Gerald Keith ; et al.	2008-03-06
Memory Chip Having an Apportionable Data Bus App 20080040529 - Bartley; Gerald Keith ; et al.	2008-02-14
Daisy Chainable Memory Chip App 20080031077 - Bartley; Gerald Keith ; et al.	2008-02-07
Daisy Chainable Memory Chip App 20080031076 - Bartley; Gerald Keith ; et al.	2008-02-07
Computer System Having Daisy Chained Memory Chips App 20080028123 - Bartley; Gerald Keith ; et al.	2008-01-31
Carrier Having Daisy Chain Of Self Timed Memory Chips App 20080028160 - Bartley; Gerald Keith ; et al.	2008-01-31
Self Timed Memory Chip Having an Apportionable Data Bus App 20080028175 - Bartley; Gerald Keith ; et al.	2008-01-31
Computer System Having Daisy Chained Self Timed Memory Chips App 20080025130 - Bartley; Gerald Keith ; et al.	2008-01-31
Memory Controller For Daisy Chained Memory Chips App 20080028158 - Bartley; Gerald Keith ; et al.	2008-01-31
Daisy Chained Memory System App 20080025129 - Bartley; Gerald Keith ; et al.	2008-01-31
Memory System Having Self Timed Daisy Chained Memory Chips App 20080028176 - Bartley; Gerald Keith ; et al.	2008-01-31
Memory Controller for Daisy Chained Self Timed Memory Chips App 20080028177 - Bartley; Gerald Keith ; et al.	2008-01-31
Carrier Having Daisy Chained Memory Chips App 20080028159 - Bartley; Gerald Keith ; et al.	2008-01-31
Memory System Having an Apportionable Data Bus and Daisy Chained Memory Chips App 20080028126 - Bartley; Gerald Keith ; et al.	2008-01-31
Computer System Having an Apportionable Data Bus App 20080028125 - Bartley; Gerald Keith ; et al.	2008-01-31
Daisy Chainable Self Timed Memory Chip App 20080028161 - Bartley; Gerald Keith ; et al.	2008-01-31
Method, Structures and Computer Program Product for Implementing Enhanced Wiring Capability for Electronic Laminate Packages App 20070294653 - Bartley; Gerald Keith ; et al.	2007-12-20
Method and power control structure for managing plurality of voltage islands App 20070138653 - Bartley; Gerald Keith ; et al.	2007-06-21
Stacking method and stacked structure for attaching memory components to associated device App 20070108611 - Bartley; Gerald Keith ; et al.	2007-05-17
Embedded probe-enabling socket with integral probe structures Grant 7,202,685 - Bartley , et al. April 10, 2	2007-04-10
Method, apparatus, and computer program product for implementing vertically coupled noise control through a mesh plane in an electronic package design App 20060236277 - Bartley; Gerald Keith ; et al.	2006-10-19
Socket assembly with incorporated memory structure Grant 7,074,050 - Bartley , et al. July 11, 2	2006-07-11

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