Mak; Tak M.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Mak; Tak M..The latest application filed is for "integrated circuit device having supports for use in a multi-dimensional die stack".
- Mak; Tak M. - Union City CA US
| Patent | Date |
|---|---|
| Current tests for I/O interface connectors Grant 9,551,741 - Thiruvengadam , et al. January 24, 2 | 2017-01-24 |
| Input/output delay testing for devices utilizing on-chip delay generation Grant 9,110,134 - Mak , et al. August 18, 2 | 2015-08-18 |
| Integrated Circuit Device Having Supports For Use In A Multi-dimensional Die Stack App 20150228635 - Mak; Tak M. | 2015-08-13 |
| Method and apparatus for an optical interconnect system Grant 8,926,196 - Detofsky , et al. January 6, 2 | 2015-01-06 |
| Method, system and apparatus for evaluation of input/output buffer circuitry Grant 8,843,794 - Nelson , et al. September 23, 2 | 2014-09-23 |
| Input/output Delay Testing For Devices Utilizing On-chip Delay Generation App 20140189457 - Mak; Tak M. ; et al. | 2014-07-03 |
| Method And Apparatus For An Optical Interconnect System App 20140093214 - DETOFSKY; Abram M. ; et al. | 2014-04-03 |
| Method, System And Apparatus For Evaluation Of Input/output Buffer Circuitry App 20140089752 - Nelson; Christopher J. ; et al. | 2014-03-27 |
| Current Tests For I/o Interface Connectors App 20130271167 - Thiruvengadam; Bharani ; et al. | 2013-10-17 |
| System pulse latch and shadow pulse latch coupled to output joining circuit Grant 7,373,572 - Mak , et al. May 13, 2 | 2008-05-13 |
| System and scanout circuits with error resilience circuit Grant 7,278,076 - Zhang , et al. October 2, 2 | 2007-10-02 |
| System and shadow circuits with output joining circuit Grant 7,278,074 - Mitra , et al. October 2, 2 | 2007-10-02 |
| Error detecting circuit Grant 7,188,284 - Mitra , et al. March 6, 2 | 2007-03-06 |
| Pseudo bus agent to support functional testing Grant 7,185,247 - Mak , et al. February 27, 2 | 2007-02-27 |
| System and shadow circuits with output joining circuit App 20060168489 - Mitra; Subhasish ; et al. | 2006-07-27 |
| System pulse latch and shadow pulse latch coupled to output joining circuit App 20060168487 - Mak; Tak M. ; et al. | 2006-07-27 |
| Testing integrated circuits using high bandwidth wireless technology App 20060052075 - Galivanche; Rajeshwar ; et al. | 2006-03-09 |
| Error detecting circuit App 20060005091 - Mitra; Subhasish ; et al. | 2006-01-05 |
| System and scanout circuits with error resilience circuit App 20060005103 - Zhang; Ming ; et al. | 2006-01-05 |
| Functional testing of logic circuits that use high-speed links Grant 6,975,954 - Mak , et al. December 13, 2 | 2005-12-13 |
| Device testing Grant 6,885,209 - Mak , et al. April 26, 2 | 2005-04-26 |
| Pseudo bus agent to support functional testing App 20040268200 - Mak, Tak M. ; et al. | 2004-12-30 |
| Functional testing of logic circuits that use high-speed links App 20040267484 - Mak, Tak M. ; et al. | 2004-12-30 |
| Memory cell structural test Grant 6,757,209 - Mak , et al. June 29, 2 | 2004-06-29 |
| Memory addressing structural test Grant 6,721,216 - Mak , et al. April 13, 2 | 2004-04-13 |
| Device testing App 20040036494 - Mak, Tak M. ; et al. | 2004-02-26 |
| Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer Grant 6,629,274 - Tripp , et al. September 30, 2 | 2003-09-30 |
| Memory addressing structural test App 20020141276 - Mak, Tak M. ; et al. | 2002-10-03 |
| Memory cell structural test App 20020141259 - Mak, Tak M. ; et al. | 2002-10-03 |
| Bus signature analyzer and behavioral functional test method Grant 6,424,926 - Mak July 23, 2 | 2002-07-23 |
| Method and apparatus for buffer self-test and characterization Grant 5,621,739 - Sine , et al. April 15, 1 | 1997-04-15 |
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