loadpatents
name:-0.022931814193726
name:-0.026586055755615
name:-0.0080399513244629
Mair; Hugh Thomas Patent Filings

Mair; Hugh Thomas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mair; Hugh Thomas.The latest application filed is for "circuit and method to measure simulation to silicon timing correlation".

Company Profile
3.24.22
  • Mair; Hugh Thomas - San Jose CA
  • Mair; Hugh Thomas - Fairview TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Frequency locked loops and related circuits and methods
Grant 11,418,203 - Mair , et al. August 16, 2
2022-08-16
Circuit And Method To Measure Simulation To Silicon Timing Correlation
App 20220170986 - Nayak; Ashish Kumar ;   et al.
2022-06-02
Frequency Locked Loops And Related Circuits And Methods
App 20220085820 - Mair; Hugh Thomas ;   et al.
2022-03-17
Method and apparatus of dual threshold clock control
Grant 10,732,701 - Yong , et al.
2020-08-04
Standard cell circuitries
Grant 10,361,190 - Dia , et al.
2019-07-23
Dynamic power meter with improved accuracy and single cycle resolution
Grant 10,345,882 - Wen , et al. July 9, 2
2019-07-09
Fast and Autonomous mechanism for CPU OC protection
Grant 10,275,010 - Mair , et al.
2019-04-30
Dual-rail power equalizer
Grant 9,690,365 - Mair , et al. June 27, 2
2017-06-27
Control method of clock gating for dithering in the clock signal to mitigate voltage transients
Grant 9,600,024 - Mair , et al. March 21, 2
2017-03-21
Fast and Autonomous Mechanism for CPU OC Protection
App 20170068296 - Mair; Hugh Thomas ;   et al.
2017-03-09
Standard Cell Circuitries
App 20170018572 - DIA; Kin-Hooi ;   et al.
2017-01-19
Dual-Rail Power Equalizer
App 20160320821 - Mair; Hugh Thomas ;   et al.
2016-11-03
Dynamic Power Meter with Improved Accuracy and Single Cycle Resolution
App 20160291068 - Wen; Huajun ;   et al.
2016-10-06
Conductive via structures for routing porosity and low via resistance, and processes of making
Grant 9,224,642 - Mair December 29, 2
2015-12-29
Conductive Via Structures For Routing Porosity And Low Via Resistance, And Processes Of Making
App 20140322867 - MAIR; Hugh Thomas
2014-10-30
Conductive via structures for routing porosity and low via resistance, and processes of making
Grant 8,872,344 - Mair October 28, 2
2014-10-28
Clock Control Method For Performance Thermal And Power Management System
App 20140095919 - Mair; Hugh Thomas ;   et al.
2014-04-03
Clock phase compensation for adjusted voltage circuits
Grant 8,564,351 - Mair , et al. October 22, 2
2013-10-22
HDMI driver tail current transistors with current mirror controlled leads
Grant 8,378,653 - Mair February 19, 2
2013-02-19
Clock Phase Compensation For Adjusted Voltage Circuits
App 20130033295 - Mair; Hugh Thomas ;   et al.
2013-02-07
Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode
Grant 8,278,980 - Dubost , et al. October 2, 2
2012-10-02
Enhancement Of Power Management Using Dynamic Voltage And Frequency Scaling And Digital Phase Lock Loop High Speed Bypass Mode
App 20120235716 - DUBOST; GILLES ;   et al.
2012-09-20
Reduced power consumption in retain-till-accessed static memories
Grant 8,218,376 - Seshadri , et al. July 10, 2
2012-07-10
Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode
Grant 8,207,764 - Dubost , et al. June 26, 2
2012-06-26
Conductive Via Structures For Routing Porosity And Low Via Resistance, And Processes Of Making
App 20110304994 - Mair; Hugh Thomas
2011-12-15
Reduced Power Consumption in Retain-Till-Accessed Static Memories
App 20110261629 - Seshadri; Anand ;   et al.
2011-10-27
Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode
App 20110095794 - Dubost; Gilles ;   et al.
2011-04-28
Component Powered by HDMI Interface
App 20110037447 - Mair; Hugh Thomas
2011-02-17
Adaptive voltage scaling with age compensation
Grant 7,793,119 - Gammie , et al. September 7, 2
2010-09-07
Systems and methods for reading data from a memory array
Grant 7,773,431 - Avramescu , et al. August 10, 2
2010-08-10
Technique for aging induced performance drift compensation in an integrated circuit
Grant 7,689,377 - Jain , et al. March 30, 2
2010-03-30
Systems And Methods For Reading Data From A Memory Array
App 20090097327 - Avramescu; Radu ;   et al.
2009-04-16
Representing data having multi-dimensional input vectors and corresponding output element by piece-wise polynomials
Grant 7,483,819 - Gurumurthy , et al. January 27, 2
2009-01-27
Systems and methods for reading data from a memory array
Grant 7,477,551 - Avramescu , et al. January 13, 2
2009-01-13
Systems and methods for managing power
Grant 7,474,582 - Mair , et al. January 6, 2
2009-01-06
Adaptive voltage scaling with age compensation
App 20080155282 - Gammie; Gordon ;   et al.
2008-06-26
Systems and methods for managing power
App 20080137444 - Mair; Hugh Thomas ;   et al.
2008-06-12
Systems and methods for reading data from a memory array
App 20080123449 - Avramescu; Radu ;   et al.
2008-05-29
Technique For Aging Induced Performance Drift Compensation In An Integrated Circuit
App 20080116455 - JAIN; PALKESH ;   et al.
2008-05-22
Representing Data Having Multi-dimensional Input Vectors and Corresponding Output Element by Piece-wise Polynomials
App 20060123074 - GURUMURTHY; Girishankar ;   et al.
2006-06-08

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