Mains; Robert E

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mains; Robert E.The latest application filed is for "technique for fast power estimation using probabilistic analysis of combinational logic".

Company Profile

0.10.5

Mains; Robert E - Morgan Hill CA
Mains; Robert E. - Morgan Hill CA
Mains; Robert E. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Verifying proper representation of semiconductor device fingers Grant 8,732,638 - Fa , et al. May 20, 2	2014-05-20
Technique for fast power estimation using probabilistic analysis of combinational logic Grant 8,380,656 - Sundaresan , et al. February 19, 2	2013-02-19
Highly threaded static timer Grant 7,958,474 - Chen , et al. June 7, 2	2011-06-07
Technique For Fast Power Estimation Using Probabilistic Analysis Of Combinational Logic App 20110106748 - Sundaresan; Krishnan ; et al.	2011-05-05
Leakage power optimization considering gate input activity and timing slack Grant 7,802,217 - Gopinath , et al. September 21, 2	2010-09-21
Multithreaded static timing analysis Grant 7,797,658 - Chen , et al. September 14, 2	2010-09-14
Highly Threaded Static Timer App 20090327985 - Chen; George J. ; et al.	2009-12-31
Multithreaded Static Timing Analysis App 20090106717 - Chen; George J. ; et al.	2009-04-23
Method for evaluating nets in crosstalk noise analysis Grant 7,216,316 - Sutherland , et al. May 8, 2	2007-05-08
Determining cycle adjustments for static timing analysis of multifrequency circuits Grant 7,206,958 - Sutherland , et al. April 17, 2	2007-04-17
Delay estimation using edge specific miller capacitances Grant 7,051,305 - Ha , et al. May 23, 2	2006-05-23
Static timing model for combinatorial gates having clock signal input App 20050177357 - Amatangelo, Matthew J. ; et al.	2005-08-11
Abstraction generation for hierarchical timing analysis using implicity connectivity graph derived from domain propagation App 20050091555 - Xiao, Tong ; et al.	2005-04-28
Automatic delay adjustment for static timing analysis using clock edge identification and half cycle paths Grant 5,771,375 - Mains June 23, 1	1998-06-23

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