loadpatents
name:-0.0056960582733154
name:-0.015450000762939
name:-0.0048589706420898
Maillard; Pierre Patent Filings

Maillard; Pierre

Patent Applications and Registrations

Patent applications and USPTO patent grants for Maillard; Pierre.The latest application filed is for "single event latch-up (sel) mitigation detect and mitigation".

Company Profile
4.12.4
  • Maillard; Pierre - Campbell CA
  • Maillard; Pierre - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Single event latch-up (SEL) mitigation detect and mitigation
Grant 10,958,067 - Maillard , et al. March 23, 2
2021-03-23
Single event latch-up (SEL) mitigation techniques
Grant 10,861,848 - Hart , et al. December 8, 2
2020-12-08
Single Event Latch-up (sel) Mitigation Detect And Mitigation
App 20200091713 - Maillard; Pierre ;   et al.
2020-03-19
Single Event Latch-up (sel) Mitigation Techniques
App 20200066713 - Hart; Michael J. ;   et al.
2020-02-27
Circuit for and method of storing data in an integrated circuit device
Grant 10,574,214 - Maillard , et al. Feb
2020-02-25
Single event upset (SEU) mitigation for FinFET technology using fin topology
Grant 10,366,999 - Maillard July 30, 2
2019-07-30
Circuit for and method of storing data in an integrated circuit device
Grant 10,263,623 - Chen , et al.
2019-04-16
Circuit for and method of enabling the selection of a circuit
Grant 10,033,388 - Rawat , et al. July 24, 2
2018-07-24
Circuit for and method of preventing multi-bit upsets induced by single event transients
Grant 9,825,632 - Maillard , et al. November 21, 2
2017-11-21
Mitigation of single event latchup
Grant 9,793,899 - Maillard , et al. October 17, 2
2017-10-17
Single Event Upset (seu) Mitigation For Finfet Technology Using Fin Topology
App 20170287919 - Maillard; Pierre
2017-10-05
Selection of logic paths for redundancy
Grant 9,484,919 - Jain , et al. November 1, 2
2016-11-01
Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit
Grant 9,281,807 - Maillard , et al. March 8, 2
2016-03-08
Integrated circuit package with thermal neutron shielding
Grant 9,236,354 - Maillard , et al. January 12, 2
2016-01-12
Integrated Circuit Package With Thermal Neutron Shielding
App 20150348915 - Maillard; Pierre ;   et al.
2015-12-03
Single-event upset mitigation in circuit design for programmable integrated circuits
Grant 9,183,338 - Jain , et al. November 10, 2
2015-11-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed