Mahmud; Tuhin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mahmud; Tuhin.The latest application filed is for "clustering simulation failures for triage and debugging".

Company Profile

1.10.11

Mahmud; Tuhin - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Clustering simulation failures for triage and debugging Grant 11,205,092 - Hickerson , et al. December 21, 2	2021-12-21
Clustering Simulation Failures For Triage And Debugging App 20200327364 - Hickerson; Bryan G. ; et al.	2020-10-15
Automatic generation of wire tag lists for a metal stack Grant 9,092,591 - Alpert , et al. July 28, 2	2015-07-28
Physical synthesis optimization with fast metric check Grant 8,881,089 - Alpert , et al. November 4, 2	2014-11-04
Automatic Generation of Wire Tag Lists for a Metal Stack App 20140223397 - Alpert; Charles J. ; et al.	2014-08-07
Automatic Generation of Wire Tag Lists for a Metal Stack App 20140195998 - Alpert; Charles J. ; et al.	2014-07-10
Automatic generation of wire tag lists for a metal stack Grant 8,769,468 - Alpert , et al. July 1, 2	2014-07-01
Resolving global coupling timing and slew violations for buffer-dominated designs Grant 8,365,120 - Alpert , et al. January 29, 2	2013-01-29
Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs App 20120144358 - Alpert; Charles J. ; et al.	2012-06-07
Concurrent buffering and layer assignment in integrated circuit layout Grant 7,895,557 - Alpert , et al. February 22, 2	2011-02-22
Slew constrained minimum cost buffering Grant 7,890,905 - Alpert , et al. February 15, 2	2011-02-15
Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout App 20090259980 - ALPERT; Charles J. ; et al.	2009-10-15
Buffer Insertion To Reduce Wirelength In Vlsi Circuits App 20090064080 - Alpert; Charles J. ; et al.	2009-03-05
Buffer insertion to reduce wirelength in VLSI circuits Grant 7,484,199 - Alpert , et al. January 27, 2	2009-01-27
Buffer Insertion To Reduce Wirelength In Vlsi Circuits App 20090013299 - Alpert; Charles J. ; et al.	2009-01-08
Slew Constrained Minimum Cost Buffering App 20080295051 - Alpert; Charles J. ; et al.	2008-11-27
Slew constrained minimum cost buffering Grant 7,448,007 - Alpert , et al. November 4, 2	2008-11-04
Slew Constrained Minimum Cost Buffering App 20080016479 - Alpert; Charles J. ; et al.	2008-01-17
System and Method of Eliminating Electrical Violations App 20070283301 - Karandikar; Arvind K. ; et al.	2007-12-06
Buffer Insertion to Reduce Wirelength in VLSI Circuits App 20070271543 - Alpert; Charles J. ; et al.	2007-11-22

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