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Patent applications and USPTO patent grants for Maheshwarla; Sreeni.The latest application filed is for "method of merging designs of an integrated circuit from a plurality of sources".
Patent | Date |
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Method of merging designs of an integrated circuit from a plurality of sources App 20070288881 - Maheshwarla; Sreeni ;   et al. | 2007-12-13 |
Self aligned method of forming non-volatile memory cells with flat word line Grant 6,878,591 - Klinger , et al. April 12, 2 | 2005-04-12 |
Electrically programmable and erasable memory cell having an improved floating gate and a method of manufacturing said floating gate and a memory device having an array of such cells made thereby App 20040238877 - Maheshwarla, Sreeni ;   et al. | 2004-12-02 |
Self aligned method of forming non-volatile memory cells with flat word line App 20030153152 - Klinger, Pavel ;   et al. | 2003-08-14 |
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