loadpatents
name:-0.048548936843872
name:-0.039604902267456
name:-0.0014638900756836
MAGRI'; Angelo Patent Filings

MAGRI'; Angelo

Patent Applications and Registrations

Patent applications and USPTO patent grants for MAGRI'; Angelo.The latest application filed is for "4h-sic electronic device with improved short-circuit performances, and manufacturing method thereof".

Company Profile
1.44.43
  • MAGRI'; Angelo - Belpasso IT
  • MAGRI'; ANGELO - Belpasso CT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
4h-sic Electronic Device With Improved Short-circuit Performances, And Manufacturing Method Thereof
App 20210399089 - SAGGIO; Mario Giuseppe ;   et al.
2021-12-23
Power Mosfet Device Having Improved Safe-operating Area And On Resistance, Manufacturing Process Thereof And Operating Method Thereof
App 20210151599 - MAGRI'; Angelo ;   et al.
2021-05-20
Electronic device of vertical MOS type with termination trenches having variable depth
Grant 10,505,033 - Magri , et al. Dec
2019-12-10
Electronic device of vertical MOS type with termination trenches having variable depth
Grant 9,647,061 - Magri , et al. May 9, 2
2017-05-09
Semiconductor structure with varying doping profile and related ICS and devices
Grant 9,627,472 - Saggio , et al. April 18, 2
2017-04-18
Integrated power device on a semiconductor substrate having an improved trench gate structure
Grant 9,520,468 - Magri' , et al. December 13, 2
2016-12-13
Electronic device of vertical MOS type with termination trenches having variable depth
Grant 9,484,404 - Barletta , et al. November 1, 2
2016-11-01
Electronic Device Of Vertical Mos Type With Termination Trenches Having Variable Depth
App 20160079356 - Magri; Angelo ;   et al.
2016-03-17
Structure For High Voltage Device And Corresponding Integration Process
App 20150349052 - SAGGIO; Mario Giuseppe ;   et al.
2015-12-03
Integrated electronic device with edge-termination structure and manufacturing method thereof
Grant 9,142,646 - Frisina , et al. September 22, 2
2015-09-22
Integrated Electronic Device With Edge-termination Structure And Manufacturing Method Thereof
App 20150187912 - FRISINA; FERRUCCIO ;   et al.
2015-07-02
Manufacturing of electronic devices in a wafer of semiconductor material having trenches with different directions
Grant 9,070,694 - Magri' , et al. June 30, 2
2015-06-30
Integrated electronic device with edge-termination structure and manufacturing method thereof
Grant 9,018,635 - Frisina , et al. April 28, 2
2015-04-28
Vertical-conduction integrated electronic device and method for manufacturing thereof
Grant 8,921,211 - Frisina , et al. December 30, 2
2014-12-30
Vertical conduction power electronic device and corresponding realization method
Grant 8,895,370 - Frisina , et al. November 25, 2
2014-11-25
Integrated Power Device On A Semiconductor Substrate Having An Improved Trench Gate Structure
App 20140138739 - MAGRI'; Angelo ;   et al.
2014-05-22
Vertical-conduction Integrated Electronic Device And Method For Manufacturing Thereof
App 20140141603 - FRISINA; Ferruccio ;   et al.
2014-05-22
Integrated power device on a semiconductor substrate having an improved trench gate structure
Grant 8,664,713 - Magri , et al. March 4, 2
2014-03-04
Vertical-conduction integrated electronic device and method for manufacturing thereof
Grant 8,653,590 - Frisina , et al. February 18, 2
2014-02-18
Vertical Conduction Power Electronic Device And Corresponding Realization Method
App 20140045309 - FRISINA; FERRUCCIO ;   et al.
2014-02-13
Method for manufacturing an integrated power device having gate structures within trenches
Grant 8,637,369 - Magri , et al. January 28, 2
2014-01-28
Power MOS electronic device and corresponding realizing method
Grant 8,482,085 - Magri , et al. July 9, 2
2013-07-09
Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof
Grant 8,420,525 - Magri' , et al. April 16, 2
2013-04-16
Power MOS electronic device and corresponding realizing method
Grant 8,420,487 - Magri , et al. April 16, 2
2013-04-16
Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof
Grant 8,405,144 - Magri' , et al. March 26, 2
2013-03-26
Process for manufacturing a large-scale integration MOS device and corresponding MOS device
Grant 8,283,702 - Salinas , et al. October 9, 2
2012-10-09
Method For Manufacturing An Integrated Power Device On A Semiconductor Substrate And Corresponding Device
App 20120220090 - MAGRI; Angelo ;   et al.
2012-08-30
Semiconductor Device With Vertical Current Flow And Low Substrate Resistance And Manufacturing Process Thereof
App 20120119382 - MAGRI'; ANGELO ;   et al.
2012-05-17
Semiconductor Device With Vertical Current Flow And Low Substrate Resistance And Manufacturing Process Thereof
App 20120119381 - MAGRI'; Angelo ;   et al.
2012-05-17
Integrated Electronic Device With Edge-termination Structure And Manufacturing Method Thereof
App 20120056200 - FRISINA; Ferruccio ;   et al.
2012-03-08
Vertical-conduction Integrated Electronic Device And Method For Manufacturing Thereof
App 20120049940 - FRISINA; Ferruccio ;   et al.
2012-03-01
Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof
Grant 8,101,991 - Magri' , et al. January 24, 2
2012-01-24
Process for manufacturing a large-scale integration MOS device and corresponding MOS device
Grant 8,030,192 - Salinas , et al. October 4, 2
2011-10-04
Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture
Grant 7,968,412 - Battiato , et al. June 28, 2
2011-06-28
Power Mos Electronic Device And Corresponding Realizing Method
App 20110089491 - Magri; Angelo ;   et al.
2011-04-21
Power Mos Electronic Device And Corresponding Realizing Method
App 20110081759 - Magri; Angelo ;   et al.
2011-04-07
Structure For High Voltage Device And Corresponding Integration Process
App 20110049638 - SAGGIO; Mario Giuseppe ;   et al.
2011-03-03
Power MOS electronic device and corresponding realizing method
Grant 7,875,936 - Magri , et al. January 25, 2
2011-01-25
Method of manufacturing a semiconductor power device
Grant 7,842,574 - Arena , et al. November 30, 2
2010-11-30
Process For Manufacturing A Large-scale Integration Mos Device And Corresponding Mos Device
App 20100237391 - SALINAS; Dario ;   et al.
2010-09-23
Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture
Grant 7,800,173 - Battiato , et al. September 21, 2
2010-09-21
Method For Manufacturing An Integrated Power Device On A Semiconductor Substrate And Corresponding Device
App 20100163978 - MAGRI; Angelo ;   et al.
2010-07-01
Manufacturing Process Of A Vertical-conduction Misfet Device With Gate Dielectric Structure Having Differentiated Thickness And Vertical-conduction Misfet Device Thus Manufacture
App 20100167481 - Battiato; Orazio ;   et al.
2010-07-01
Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices
Grant 7,713,853 - Frisina , et al. May 11, 2
2010-05-11
Switching-controlled power MOS electronic device
Grant 7,569,883 - Frisina , et al. August 4, 2
2009-08-04
Insulated gate planar integrated power device with co-integrated Schottky diode and process
Grant 7,560,368 - Magri' , et al. July 14, 2
2009-07-14
Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture
App 20080211021 - Battiato; Orazio ;   et al.
2008-09-04
Method Of Manufacturing A Semiconductor Power Device
App 20080211015 - Arena; Giuseppe ;   et al.
2008-09-04
Method For Manufacturing Electronic Devices Integrated In A Semiconductor Substrate And Corresponding Devices
App 20080169517 - Frisina; Ferrucio ;   et al.
2008-07-17
Vertical conduction power electronic device package and corresponding assembling method
Grant 7,372,142 - Ferrara , et al. May 13, 2
2008-05-13
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density
Grant 7,304,335 - Magri' , et al. December 4, 2
2007-12-04
Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof
App 20070272980 - Magri; Angelo ;   et al.
2007-11-29
Process for manufacturing a large-scale integration MOS device and corresponding MOS device
App 20070161217 - Salinas; Dario ;   et al.
2007-07-12
Insulated gate planar integrated power device with co-integrated Schottky diode and process
App 20070102725 - Magri'; Angelo ;   et al.
2007-05-10
Semiconductor power device with insulated gate and trench-gate structure and corresponding manufacturing method
Grant 7,205,607 - Alessandria , et al. April 17, 2
2007-04-17
Semiconductor Power Device With Insulated Gate Formed In A Trench, And Manufacturing Process Thereof
App 20070063272 - Arena; Giuseppe ;   et al.
2007-03-22
Power MOS electronic device and corresponding realizing method
App 20060244059 - Magri; Angelo ;   et al.
2006-11-02
Method for enhancing the electric connection between a power electronic device and its package
Grant 7,126,173 - Frisina , et al. October 24, 2
2006-10-24
Switching-controlled power MOS electronic device
App 20060220121 - Frisina; Ferruccio ;   et al.
2006-10-05
Vertical-conduction And Planar-structure Mos Device With A Double Thickness Of Gate Oxide And Method For Realizing Power Vertical Mos Transistors With Improved Static And Dynamic Performance And High Scaling Down Density
App 20060186434 - MAGRI'; Angelo ;   et al.
2006-08-24
MOS power device with high integration density and manufacturing process thereof
Grant 7,091,558 - Frisina , et al. August 15, 2
2006-08-15
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density
Grant 7,067,363 - Magri' , et al. June 27, 2
2006-06-27
Vertical conduction power electronic device and corresponding realization method
App 20060071242 - Frisina; Ferruccio ;   et al.
2006-04-06
Vertical conduction power electronic device package and corresponding assembling method
App 20050275082 - Ferrara, Maurizio Maria ;   et al.
2005-12-15
Semiconductor power device with insulated gate and trench-gate structure and corresponding manufacturing method
App 20050145977 - Alessandria, Antonino Sebastiano ;   et al.
2005-07-07
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density
App 20050139906 - Magri', Angelo ;   et al.
2005-06-30
MOS power device with high integration density and manufacturing process thereof
App 20040222483 - Frisina, Ferruccio ;   et al.
2004-11-11
Insulated gate planar integrated power device with co-integrated schottky diode and process
App 20040164304 - Magri, Angelo ;   et al.
2004-08-26
Method for enhancing the electric connection between a power electronic device and its package
App 20030100154 - Frisina, Ferruccio ;   et al.
2003-05-29
High integration density MOS technology power device structure
Grant 6,492,691 - Magri' , et al. December 10, 2
2002-12-10
Electronic device integrating an insulated gate bipolar transistor power device and a diode into a protective package
App 20020113247 - Magri, Angelo ;   et al.
2002-08-22
High Integration Density Mos Technology Power Device Structure
App 20020113276 - MAGRI', ANGELO ;   et al.
2002-08-22
MOS technology power device
Grant 6,404,010 - Saggio , et al. June 11, 2
2002-06-11
MOS technology power device
App 20020014671 - Saggio, Mario ;   et al.
2002-02-07
Single Feature Size Mos Technology Power Device
App 20010011722 - FRISINA, FERRUCCIO ;   et al.
2001-08-09
Single Feature Size Mos Technology Power Device
App 20010012663 - MAGRI', ANGELO ;   et al.
2001-08-09
High Density Mos Technology Power Device
App 20010012654 - MAGRI', ANGELO ;   et al.
2001-08-09
Asymmetric MOS technology power device
App 20010001213 - Magri', Angelo ;   et al.
2001-05-17
Process for integrating, in a single semiconductor chip, MOS technology devices with different threshold voltages
Grant 6,040,609 - Frisina , et al. March 21, 2
2000-03-21

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