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Exception Handling In Transactions
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Testing Bit Values Inside Vector Elements
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Address Translation Data Invalidation
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Replicate Partition Instruction
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Replicate Elements Instruction
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Permission Control For Contingent Memory Access Program Instruction
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Vector Processing Using Loops Of Dynamic Vector Length
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Profiling Asynchronous Events Resulting From The Execution Of Software At Code Region Granularity
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Instruction and logic for optimization level aware branch prediction
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Instruction and logic for bulk register reclamation
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Vector Length Querying Instruction
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Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region
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Managed instruction cache prefetching
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Double rounded combined floating-point multiply and add
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Double Rounded Combined Floating-point Multiply And Add
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Double rounded combined floating-point multiply and add
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Combined floating point multiplier adder with intermediate rounding logic
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Image signal processor with a block checking circuit
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Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs
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Instruction And Logic For Bulk Register Reclamation
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Double Rounded Combined Floating-point Multiply And Add
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Double rounded combined floating-point multiply and add
Grant 9,213,523 - Samudrala , et al. December 15, 2 | 2015-12-15 |
Image Signal Processor With A Block Checking Circuit
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Frequency and voltage scaling architecture
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Mechanism For Facilitating Dynamic And Efficient Fusion Of Computing Instructions In Software Programs
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Combined Floating Point Multiplier Adder With Intermediate Rounding Logic
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Frequency And Voltage Scaling Architecture
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Method, Apparatus And System For Selective Execution Of A Commit Instruction
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Instruction And Logic For Optimization Level Aware Branch Prediction
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Frequency and voltage scaling architecture
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Managed Instruction Cache Prefetching
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Double Rounded Combined Floating-point Multiply And Add
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Replacement policy for hot code detection
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Thread Migration To Improve Power Efficiency In A Parallel Processing Environment
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Support For Speculative Ownership Without Data
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Frequency And Voltage Scaling Architecture
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Frequency and voltage scaling architecture
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Achieving coherence between dynamically optimized code and original code
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Thread migration to improve power efficiency in a parallel processing environment
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Thread Migration To Improve Power Efficiency In A Parallel Processing Environment
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Thread migration to improve power efficiency in a parallel processing environment
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Leakage power estimation
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Replacement Policy For Hot Code Detection
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Compressing address communications between processors
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Meeting point thread characterization
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Thread Migration To Improve Power Efficiency In A Parallel Processing Environment
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Achieving Coherence Between Dynamically Optimized Code And Original Code
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Compressing address communications between processors
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Frequency and voltage scaling architecture
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Frequency and voltage scaling architecture
Grant 7,434,073 - Magklis , et al. October 7, 2 | 2008-10-07 |
Leakage Power Estimation
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Meeting point thread characterization
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Multiple clock domain microprocessor
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Multiple clock domain microprocessor
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Frequency and voltage scaling architecture
App 20060117202 - Magklis; Grigorios ; et al. | 2006-06-01 |
Multiple clock domain microprocessor
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