MAGERA; JAROSLAW A.
Patent Applications and Registrations
Patent applications and USPTO patent grants for MAGERA; JAROSLAW A..The latest application filed is for "method of filling vias with fusible metal".
- MAGERA; JAROSLAW A. - PALATINE IL
| Patent | Date |
|---|---|
| Method Of Filling Vias With Fusible Metal App 20090218124 - MAGERA; JAROSLAW A. ; et al. | 2009-09-03 |
| Printed circuit board having closed vias Grant 7,557,304 - Magera , et al. July 7, 2 | 2009-07-07 |
| Printed circuit board Grant 7,459,202 - Magera , et al. December 2, 2 | 2008-12-02 |
| Method for fabricating a printed circuit board Grant 7,451,540 - Magera , et al. November 18, 2 | 2008-11-18 |
| Method for fabricating closed vias in a printed circuit board Grant 7,427,562 - Magera , et al. September 23, 2 | 2008-09-23 |
| Methods For Making Printed Wiring Boards App 20080148561 - Magera; Jaroslaw A. ; et al. | 2008-06-26 |
| Printed Circuit Board Having Closed Vias App 20080121420 - Magera; Jaroslaw A. ; et al. | 2008-05-29 |
| Method For Fabricating Closed Vias In A Printed Circuit Board App 20080119041 - Magera; Jaroslaw A. ; et al. | 2008-05-22 |
| Method For Fabricating A Printed Circuit Board App 20080092376 - Magera; Jaroslaw A. ; et al. | 2008-04-24 |
| Capacitance laminate and printed circuit board apparatus and method Grant 7,361,847 - Dunn , et al. April 22, 2 | 2008-04-22 |
| Printed Circuit Board App 20080003414 - Magera; Jaroslaw A. ; et al. | 2008-01-03 |
| Capacitance laminate and printed circuit board apparatus and method App 20070151758 - Dunn; Gregory J. ; et al. | 2007-07-05 |
| Printed circuit patterned embedded capacitance layer Grant 7,138,068 - Dunn , et al. November 21, 2 | 2006-11-21 |
| Printed circuit patterned embedded capacitance layer App 20060207970 - Dunn; Gregory J. ; et al. | 2006-09-21 |
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