| Patent | Date |
|---|
Method for producing a plurality of layers of metallurgy
Grant 4,805,683 - Magdo , et al. February 21, 1 | 1989-02-21 |
Self-aligned metal process for integrated circuit metallization
Grant 4,758,528 - Goth , et al. * July 19, 1 | 1988-07-19 |
Method for manufacturing vertical PNP transistor with shallow emitter
Grant 4,534,806 - Magdo August 13, 1 | 1985-08-13 |
Self-aligned metal field effect transistor integrated circuit
Grant 4,513,303 - Abbas , et al. April 23, 1 | 1985-04-23 |
Complementary transistor structure and method for manufacture
Grant 4,485,552 - Magdo , et al. December 4, 1 | 1984-12-04 |
Method of making emitter regions by implantation through a non-monocrystalline layer
Grant 4,452,645 - Chu , et al. June 5, 1 | 1984-06-05 |
Method to fabricate stud structure for self-aligned metallization
Grant 4,424,621 - Abbas , et al. January 10, 1 | 1984-01-10 |
Self-aligned metal process for integrated circuit metallization
Grant 4,400,865 - Goth , et al. August 30, 1 | 1983-08-30 |
Dielectrically isolated semiconductor devices
Grant 4,396,933 - Magdo , et al. August 2, 1 | 1983-08-02 |
Self-aligned metal process for field effect transistor integrated circuits
Grant 4,359,816 - Abbas , et al. November 23, 1 | 1982-11-23 |
Self-aligned metal process for integrated injection logic integrated circuits
Grant 4,322,883 - Abbas , et al. April 6, 1 | 1982-04-06 |
Integrated circuit structures with full dielectric isolation and a novel method for fabrication thereof
Grant 4,261,003 - Magdo , et al. April 7, 1 | 1981-04-07 |
Method for making a silicon mask
Grant 4,256,532 - Magdo , et al. March 17, 1 | 1981-03-17 |
Process of making field effect transistor having improved threshold stability by ion-implantation
Grant 4,154,626 - Joy , et al. May 15, 1 | 1979-05-15 |
Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions
Grant 4,149,915 - Bohg , et al. April 17, 1 | 1979-04-17 |
Epitaxial process for the fabrication of a field effect transistor having improved threshold stability
Grant 4,089,712 - Joy , et al. May 16, 1 | 1978-05-16 |
Method for forming integrated circuit regions defined by recessed dielectric isolation
Grant 4,044,454 - Magdo August 30, 1 | 1977-08-30 |
Field effect transistor having improved threshold stability
Grant 4,028,717 - Joy , et al. June 7, 1 | 1977-06-07 |
Integrated circuit chip carrier and method for forming the same
Grant 4,023,197 - Magdo , et al. May 10, 1 | 1977-05-10 |
Semiconductor resistor having a high value resistance for use in an integrated circuit semiconductor device
Grant 4,005,471 - Magdo , et al. January 25, 1 | 1977-01-25 |
Dielectrically isolated Schottky Barrier structure and method of forming the same
Grant 3,956,527 - Magdo , et al. May 11, 1 | 1976-05-11 |
Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
Grant 3,954,523 - Magdo , et al. May 4, 1 | 1976-05-04 |
Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation
Grant 3,944,447 - Magdo , et al. March 16, 1 | 1976-03-16 |
Integrated circuit chip carrier and method for forming the same
Grant 3,918,148 - Magdo , et al. November 11, 1 | 1975-11-11 |
Method for fabricating minute openings in insulating layers during the formation of integrated circuits
Grant 3,904,454 - Magdo , et al. September 9, 1 | 1975-09-09 |
Novel integratable Schottky barrier structure and method for the fabrication thereof
Grant 3,900,344 - Magdo August 19, 1 | 1975-08-19 |
Method for making a space charge limited transistor having recessed dielectric isolation
Grant 3,894,891 - Magdo , et al. July 15, 1 | 1975-07-15 |
Method Of Fabricating Integrated Circuit Device Structure With Complementary Elements Utilizing Selective Thermal Oxidation And Selective Epitaxial Deposition
Grant 3,861,968 - Magdo , et al. January 21, 1 | 1975-01-21 |
Dielectrically Isolated Schottky Barrier Structure And Method Of Forming The Same
Grant 3,858,231 - Magdo , et al. December 31, 1 | 1974-12-31 |
Space Charge Limited Transistor Having Recessed Dielectric Isolation
Grant 3,855,609 - Magdo , et al. December 17, 1 | 1974-12-17 |
An Integrated Circuit Test Transistor Structure And Method Of Fabricating The Same
Grant 3,774,088 - Magdo , et al. November 20, 1 | 1973-11-20 |
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