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Patent applications and USPTO patent grants for Maemura; Kouji.The latest application filed is for "cache memory having improved hit ratio by selecting the number of bus cycles required for block replacement".
Patent | Date |
---|---|
Cache memory having improved hit ratio by selecting the number of bus cycles required for block replacement Grant 5,559,985 - Maemura September 24, 1 | 1996-09-24 |
Microcomputer development support system operable with only background monitor and without cache replacement Grant 5,544,307 - Maemura August 6, 1 | 1996-08-06 |
Cache memory unit including a replacement address register and address update circuitry for reduced cache overhead Grant 5,535,350 - Maemura July 9, 1 | 1996-07-09 |
Debugger operable with only background monitor Grant 5,455,936 - Maemura October 3, 1 | 1995-10-03 |
Microprogram controller including leading microinstruction from a generator executed while succeeding microinstruction from memory is read out Grant 5,247,624 - Koumoto , et al. September 21, 1 | 1993-09-21 |
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