Madhyastha; Sadhana
Patent Applications and Registrations
Patent applications and USPTO patent grants for Madhyastha; Sadhana.The latest application filed is for "word line transistor stacking for leakage control".
- Madhyastha; Sadhana - Los Altos CA
- Madhyastha; Sadhana - Santa Clara CA
| Patent | Date |
|---|---|
| Word line transistor stacking for leakage control Grant 6,914,848 - Jamshidi , et al. July 5, 2 | 2005-07-05 |
| Word line transistor stacking for leakage control App 20040252574 - Jamshidi, Shahram ; et al. | 2004-12-16 |
| Low power precharge scheme for memory bit lines Grant 6,631,093 - Kumar , et al. October 7, 2 | 2003-10-07 |
| Multi-entry register cell Grant 6,628,539 - Kumar , et al. September 30, 2 | 2003-09-30 |
| Method and apparatus for low power memory bit line precharge Grant 6,629,194 - Kumar , et al. September 30, 2 | 2003-09-30 |
| Low Power Precharge Scheme For Memory Bit Lines App 20030002382 - Kumar, Sudarshan ; et al. | 2003-01-02 |
| Multi-entry register cell App 20020181268 - Kumar, Sudarshan ; et al. | 2002-12-05 |
| Method and apparatus for low power memory bit line precharge App 20020184431 - Kumar, Sudarshan ; et al. | 2002-12-05 |
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