| Patent | Date |
|---|
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
Grant RE40,921 - Wu , et al. September 22, 2 | 2009-09-22 |
Method and apparatus for performing deferred transactions
Grant RE38,388 - Sarangdhar , et al. January 13, 2 | 2004-01-13 |
Memory expansion channel for propagation of control and request packets
Grant 6,633,947 - Holman , et al. October 14, 2 | 2003-10-14 |
Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system
Grant 6,598,103 - MacWilliams , et al. July 22, 2 | 2003-07-22 |
Method and apparatus for implementing multiple memory buses on a memory module
Grant 6,587,912 - Leddige , et al. July 1, 2 | 2003-07-01 |
Method and apparatus for detecting errors in data output from memory and a device failure in the memory
Grant 6,519,735 - Holman , et al. February 11, 2 | 2003-02-11 |
Method and apparatus for supporting multiple overlapping address spaces on a shared bus
App 20020166039 - MacWilliams, Peter D. ; et al. | 2002-11-07 |
Method for implementing multiple memory buses on a memory module
Grant 6,477,614 - Leddige , et al. November 5, 2 | 2002-11-05 |
Data flow control mechanism for a bus supporting two-and three-agent transactions
Grant 6,405,271 - MacWilliams , et al. June 11, 2 | 2002-06-11 |
Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system
App 20020065967 - MacWilliams, Peter D. ; et al. | 2002-05-30 |
Method And Apparatus For Implementing Multiple Memory Buses On A Memory Module
App 20020038405 - LEDDIGE, MICHAEL W. ; et al. | 2002-03-28 |
Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
Grant 6,336,159 - MacWilliams , et al. January 1, 2 | 2002-01-01 |
Method and apparatus for supporting multiple overlapping address spaces on a shared bus
App 20010014935 - MacWilliams, Peter D. ; et al. | 2001-08-16 |
Method and apparatus for retrieving data from a data storage device
App 20010011317 - Bonella, Randy M. ; et al. | 2001-08-02 |
Apparatus and method for bus timing compensation
Grant 6,226,757 - Ware , et al. May 1, 2 | 2001-05-01 |
Independent timing compensation of write data path and read data path on a common data bus
Grant 6,128,748 - MacWilliams , et al. October 3, 2 | 2000-10-03 |
Method and apparatus for sharing a signal line between agents
Grant 6,112,016 - MacWilliams , et al. August 29, 2 | 2000-08-29 |
High performance cost optimized memory with delayed memory writes
Grant 6,075,730 - Barth , et al. June 13, 2 | 2000-06-13 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
Grant 5,961,621 - Wu , et al. October 5, 1 | 1999-10-05 |
Method and apparatus for executing multiple transactions within a single arbitration cycle
Grant 5,948,094 - Solomon , et al. September 7, 1 | 1999-09-07 |
Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
Grant 5,919,254 - Pawlowski , et al. July 6, 1 | 1999-07-06 |
Method and apparatus for changing data transfer widths in a computer system
Grant 5,911,053 - Pawlowski , et al. June 8, 1 | 1999-06-08 |
Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
Grant 5,905,876 - Pawlowski , et al. May 18, 1 | 1999-05-18 |
Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
Grant 5,906,001 - Wu , et al. May 18, 1 | 1999-05-18 |
Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation
Grant 5,903,916 - Pawlowski , et al. May 11, 1 | 1999-05-11 |
Method and apparartus for sharing a signal line between agents
Grant 5,822,767 - MacWilliams , et al. October 13, 1 | 1998-10-13 |
Highly pipelined bus architecture
Grant 5,796,977 - Sarangdhar , et al. August 18, 1 | 1998-08-18 |
Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
Grant 5,784,579 - Pawlowski , et al. July 21, 1 | 1998-07-21 |
Scalable cache attributes for an input/output bus
Grant 5,651,137 - MacWilliams , et al. July 22, 1 | 1997-07-22 |
Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
Grant 5,625,779 - Solomon , et al. April 29, 1 | 1997-04-29 |
Asynchronous modular bus architecture with cache consistency
Grant 5,537,640 - Pawlowski , et al. July 16, 1 | 1996-07-16 |
Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset
Grant 5,513,331 - Pawlowski , et al. April 30, 1 | 1996-04-30 |
Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer
Grant 5,471,637 - Pawlowski , et al. November 28, 1 | 1995-11-28 |
Second level cache controller unit and system
Grant 5,355,467 - MacWilliams , et al. October 11, 1 | 1994-10-11 |
Optimized write protocol for memory accesses utilizing row and column strobes
Grant 5,301,299 - Pawlowski , et al. April 5, 1 | 1994-04-05 |
Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
Grant 5,293,603 - MacWilliams , et al. March 8, 1 | 1994-03-08 |
Two strobed memory access
Grant 5,239,638 - Pawlowski , et al. August 24, 1 | 1993-08-24 |
Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
Grant 5,228,134 - MacWilliams , et al. July 13, 1 | 1993-07-13 |
Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit
Grant 4,785,396 - Murphy , et al. November 15, 1 | 1988-11-15 |
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