Ma; William Hsioh-Lien

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ma; William Hsioh-Lien.The latest application filed is for "high-voltage silicon-on-insulator transistors and methods of manufacturing the same".

Company Profile

0.14.7

Ma; William Hsioh-Lien - Fishkill NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High-voltage silicon-on-insulator transistors and methods of manufacturing the same Grant 8,772,876 - Ma , et al. July 8, 2	2014-07-08
High-voltage silicon-on-insulator transistors and methods of manufacturing the same Grant 7,790,527 - Ma , et al. September 7, 2	2010-09-07
High-voltage Silicon-on-insulator Transistors And Methods Of Manufacturing The Same App 20080048263 - Ma; William Hsioh-Lien ; et al.	2008-02-28
High-voltage silicon-on-insulator transistors and methods of manufacturing the same App 20070182030 - Ma; William Hsioh-Lien ; et al.	2007-08-09
Method of managing attached document Grant 6,915,333 - Delia , et al. July 5, 2	2005-07-05
Method of designating multiple hypertext links to be sequentially viewed Grant 6,788,316 - Ma , et al. September 7, 2	2004-09-07
Method of sending an email to a plurality of recipients with selective treatment of attached files App 20030225837 - Delia, Wayne M. ; et al.	2003-12-04
Method of managing attached document App 20030115273 - Delia, Wayne M. ; et al.	2003-06-19
Semiconductor with nanoscale features Grant 6,506,660 - Holmes , et al. January 14, 2	2003-01-14
Semiconductor capacitors App 20020058394 - Holmes, Steven J. ; et al.	2002-05-16
Method for increasing the capacitance of a semiconductor capacitors Grant 6,358,813 - Holmes , et al. March 19, 2	2002-03-19
Multistack 3-dimensional high density semiconductor device and method for fabrication App 20020000615 - Ma, William Hsioh-Lien ; et al.	2002-01-03
Multistack 3-dimensional high density semiconductor device and method for fabrication Grant 6,291,858 - Ma , et al. September 18, 2	2001-09-18
Method of fabricating trench for soi merged logic dram App 20010001719 - Hakey, Mark Charles ; et al.	2001-05-24
Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation Grant 6,025,242 - Ma , et al. February 15, 2	2000-02-15
Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions Grant 6,022,771 - Ma , et al. February 8, 2	2000-02-08
Fabrication of semiconductor device having shallow junctions Grant 5,998,273 - Ma , et al. December 7, 1	1999-12-07
Method for forming cornered images on a substrate and photomask formed thereby Grant 5,959,325 - Adair , et al. September 28, 1	1999-09-28
Microelectronic package and fabrication thereof Grant 5,923,090 - Fallon , et al. July 13, 1	1999-07-13
Trench storage dram cell including a step transfer device Grant 5,831,301 - Horak , et al. November 3, 1	1998-11-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.