Ma; William H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ma; William H..The latest application filed is for "dual gate logic device".

Company Profile

0.23.8

Ma; William H. - Fishkill NY
Ma; William H. - Wappingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Increased capacitance trench capacitor Grant 6,936,879 - Furukawa , et al. August 30, 2	2005-08-30
Dual gate logic device Grant 6,891,226 - Furukawa , et al. May 10, 2	2005-05-10
Dual gate logic device App 20030201500 - Furukawa, Toshiharu ; et al.	2003-10-30
Increased capacitance trench capacitor Grant 6,620,675 - Furukawa , et al. September 16, 2	2003-09-16
Increased capacitance trench capacitor App 20030170952 - Furukawa, Toshiharu ; et al.	2003-09-11
Method of manufacturing dual gate logic devices Grant 6,596,597 - Furukawa , et al. July 22, 2	2003-07-22
Increased capacitance trench capacitor App 20030060005 - Furukawa, Toshiharu ; et al.	2003-03-27
Activating in-situ doped gate on high dielectric constant materials App 20030025167 - Park, Heemyong ; et al.	2003-02-06
Method of fabricating SiO2 spacers and annealing caps Grant 6,512,266 - Deshpande , et al. January 28, 2	2003-01-28
Method Of Fabricating Sio2 Spacers And Annealing Caps App 20030011080 - Deshpande, Sadanand V. ; et al.	2003-01-16
Dual gate logic device App 20020187610 - Furukawa, Toshiharu ; et al.	2002-12-12
Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer Grant 6,333,245 - Furukawa , et al. December 25, 2	2001-12-25
Dram Cell With Active Area Reclaim App 20010042880 - DIVAKARUNI, RAMA ; et al.	2001-11-22
Method of fabricating a stack capacitor DRAM App 20010035551 - Kotecki, David E. ; et al.	2001-11-01
Process for building borderless bitline, wordline amd DRAM structure Grant 6,261,933 - Hakey , et al. July 17, 2	2001-07-17
DRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate Grant 6,262,450 - Kotecki , et al. July 17, 2	2001-07-17
Trench storage dynamic random access memory cell with vertical transfer device Grant 6,225,158 - Furukawa , et al. May 1, 2	2001-05-01
Resist image reversal by means of spun-on-glass Grant 6,221,562 - Boyd , et al. April 24, 2	2001-04-24
Method for manufacturing high performance MOSFET device with raised source and drain Grant 6,207,540 - Furukawa , et al. March 27, 2	2001-03-27
Method for a controlled bottle trench for a dram storage node Grant 6,190,988 - Furukawa , et al. February 20, 2	2001-02-20
Trench storage dynamic random access memory cell with vertical transfer device Grant 6,184,549 - Furukawa , et al. February 6, 2	2001-02-06
Process for building borderless bitline, wordline and DRAM structure and resulting structure Grant 6,175,128 - Hakey , et al. January 16, 2	2001-01-16
Trench separator for self-defining discontinuous film Grant 6,150,230 - Kotecki , et al. November 21, 2	2000-11-21
Method for varying x-ray hybrid resist space dimensions Grant 6,014,422 - Boyd , et al. January 11, 2	2000-01-11
Adherent separator for self-defining discontinuous film Grant 6,002,575 - Kotecki , et al. December 14, 1	1999-12-14
Five square vertical dynamic random access memory cell Grant 5,949,700 - Furukawa , et al. September 7, 1	1999-09-07
Overhanging separator for self-defining stacked capacitor Grant 5,796,573 - Kotecki , et al. August 18, 1	1998-08-18
Fabrication method for high-capacitance storage node structures Grant 5,776,660 - Hakey , et al. July 7, 1	1998-07-07
Isolated sidewall capacitor with dual dielectric Grant 5,585,998 - Kotecki , et al. December 17, 1	1996-12-17
Method for passivating an undercut in semiconductor device preparation Grant 4,667,395 - Ahlgren , et al. May 26, 1	1987-05-26
Cathode for etching Grant 4,350,578 - Frieser , et al. September 21, 1	1982-09-21

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