Lye; William Michael

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lye; William Michael.The latest application filed is for "radio frequency flash adc circuits".

Company Profile

3.22.6

Lye; William Michael - Coquitlam CA
Lye; William Michael - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Radio frequency flash ADC circuits Grant 10,587,281 - Lye , et al.	2020-03-10
Digital-to-analog converter system and method Grant 10,326,468 - Lye , et al.	2019-06-18
Radio Frequency Flash Adc Circuits App 20190036539 - LYE; William Michael ; et al.	2019-01-31
Radio frequency flash ADC circuits Grant 10,141,945 - Lye , et al. Nov	2018-11-27
Digital-To-Analog Converter System And Method App 20180191368 - LYE; William Michael ; et al.	2018-07-05
Radio Frequency Flash Adc Circuits App 20180091166 - LYE; William Michael ; et al.	2018-03-29
Digital-to-analog converter system and method Grant 9,906,236 - Lye , et al. February 27, 2	2018-02-27
Radio frequency flash ADC circuits Grant 9,847,788 - Lye , et al. December 19, 2	2017-12-19
Digital-to-analog Converter System And Method App 20170134037 - LYE; William Michael ; et al.	2017-05-11
Radio Frequency Flash Adc Circuits App 20170054448 - LYE; William Michael ; et al.	2017-02-23
Digital to-analog converter system and method Grant 9,413,394 - Lye , et al. August 9, 2	2016-08-09
Low-noise flexible frequency clock generation from two fixed-frequency references Grant 9,231,600 - Djahanshahi , et al. January 5, 2	2016-01-05
Low-noise flexible frequency clock generation from two fixed-frequency references Grant 9,225,508 - Lye , et al. December 29, 2	2015-12-29
System and method for synchronizing local oscillators Grant 9,225,507 - Lye , et al. December 29, 2	2015-12-29
Low-noise flexible frequency clock generation from two fixed-frequency references Grant 9,215,062 - Djahanshahi , et al. December 15, 2	2015-12-15
Scrambler with built in test capabilities for unary DAC Grant 9,124,287 - Ho , et al. September 1, 2	2015-09-01
Low-noise flexible frequency clock generation from two fixed-frequency references Grant 9,112,517 - Lye , et al. August 18, 2	2015-08-18
Quantization noise-shaping device Grant 9,094,033 - Lye July 28, 2	2015-07-28
Interleaved digital to analog conversion Grant 8,773,296 - Dusatko , et al. July 8, 2	2014-07-08
DSP-based diagnostics for monitoring a SerDes link Grant 8,467,436 - Warner , et al. June 18, 2	2013-06-18
Jitter attenuation with a fractional-N clock synthesizer Grant 7,986,190 - Lye July 26, 2	2011-07-26
Configurable voltage mode transmitted architecture with common-mode adjustment and novel pre-emphasis Grant 7,501,851 - Venditti , et al. March 10, 2	2009-03-10
Configurable Voltage Mode Transmitted Architecture With Common-Mode Adjustment And Novel Pre-Emphasis App 20070285120 - Venditti; Michael Ben ; et al.	2007-12-13
Systems and methods for actively-peaked current-mode logic Grant 7,288,971 - Plasterer , et al. October 30, 2	2007-10-30
Systems and methods for translation of signal levels across voltage domains Grant 7,205,820 - Yeung , et al. April 17, 2	2007-04-17
Systems and methods for actively-peaked current-mode logic Grant 7,202,706 - Plasterer , et al. April 10, 2	2007-04-10
Joint equalization and timing acquisition for RZ signals Grant 7,023,941 - Rey , et al. April 4, 2	2006-04-04

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