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name:-0.010462045669556
name:-0.0019619464874268
Lustig; Naftali Eliahu Patent Filings

Lustig; Naftali Eliahu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lustig; Naftali Eliahu.The latest application filed is for "crack bifurcation in back-end-of-line".

Company Profile
1.11.11
  • Lustig; Naftali Eliahu - Croton on Hudson NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Crack bifurcation in back-end-of-line
Grant 11,133,268 - Sinha , et al. September 28, 2
2021-09-28
Crack Bifurcation In Back-end-of-line
App 20200373250 - SINHA; TUHIN ;   et al.
2020-11-26
Electronic fuse vias in interconnect structures
Grant 9,099,468 - Bao , et al. August 4, 2
2015-08-04
Electronic Fuse Vias In Interconnect Structures
App 20150041951 - Bao; Junjing ;   et al.
2015-02-12
Electronic fuse vias in interconnect structures
Grant 8,916,461 - Bao , et al. December 23, 2
2014-12-23
Fuse and integrated conductor
Grant 8,836,124 - Bonilla , et al. September 16, 2
2014-09-16
Electronic anti-fuse
Grant 8,736,020 - Bao , et al. May 27, 2
2014-05-27
Electronic Fuse Vias in Interconnect Structures
App 20140077334 - Bao; Jinjing ;   et al.
2014-03-20
Electronic Anti-fuse
App 20140070363 - Bao; Junjing ;   et al.
2014-03-13
Fuse and Integrated Conductor
App 20130234284 - Bonilla; Griselda ;   et al.
2013-09-12
Semiconductor structure
Grant 8,030,707 - Cheng , et al. October 4, 2
2011-10-04
Method For Forming A Semiconductor Structure To Remedy Box Undercut And Structure Formed Thereby
App 20100213522 - Cheng; Kangguo ;   et al.
2010-08-26
Method Of Forming A Dual-damascene Structure Using An Underlayer
App 20090093114 - Burns; Sean David ;   et al.
2009-04-09
Interconnect structure and process of making the same
Grant 7,488,679 - Standaert , et al. February 10, 2
2009-02-10
Interconnect Structure And Process Of Making The Same
App 20080026568 - Standaert; Theodorus Eduardus ;   et al.
2008-01-31
Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect
Grant 6,573,606 - Sambucetti , et al. June 3, 2
2003-06-03
Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect
App 20030001275 - Sambucetti, Carlos Juan ;   et al.
2003-01-02
Method and apparatus for in-line oxide thickness determination in chemical-mechanical polishing
Grant 6,020,264 - Lustig , et al. February 1, 2
2000-02-01

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