loadpatents
name:-0.0053169727325439
name:-0.013713836669922
name:-0.00057697296142578
Lussier; Daniel J. Patent Filings

Lussier; Daniel J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lussier; Daniel J..The latest application filed is for "method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task".

Company Profile
0.12.3
  • Lussier; Daniel J. - Holliston MA
  • Lussier; Daniel J. - Bellingham MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuit that processes communication packets with a buffer management engine having a pointer cache
Grant RE42,092 - Tompkins , et al. February 1, 2
2011-02-01
Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task
Grant 7,099,328 - Galbi , et al. August 29, 2
2006-08-29
Integrated circuit that processes communication packets with a buffer management engine having a pointer cache
Grant 7,046,686 - Tompkins , et al. May 16, 2
2006-05-16
Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters
Grant 6,888,830 - Snyder II , et al. May 3, 2
2005-05-03
Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
Grant 6,822,959 - Galbi , et al. November 23, 2
2004-11-23
Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task
App 20040202192 - Galbi, Duane E. ;   et al.
2004-10-14
Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information
Grant 6,804,239 - Lussier , et al. October 12, 2
2004-10-12
Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels
Grant 6,760,337 - Snyder, II , et al. July 6, 2
2004-07-06
Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor
Grant 6,754,223 - Lussier , et al. June 22, 2
2004-06-22
Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
App 20020057708 - Galbi, Duane E. ;   et al.
2002-05-16
Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task
App 20020051460 - Galbi, Duane E. ;   et al.
2002-05-02
Asynchronous transfer mode cell processing system with scoreboard scheduling
Grant 6,359,891 - Bergantino , et al. March 19, 2
2002-03-19
Asynchronous transfer mode cell processing system with scoreboard scheduling
Grant 6,128,303 - Bergantino , et al. October 3, 2
2000-10-03
Asynchronous transfer mode cell processing system with multiple cell source multiplexing
Grant 5,748,631 - Bergantino , et al. May 5, 1
1998-05-05
Asynchronous transfer mode cell processing system with load multiple instruction and memory write-back
Grant 5,748,630 - Bergantino , et al. May 5, 1
1998-05-05

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