| Patent | Date |
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Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
Grant 10,186,524 - Pritchard , et al. Ja | 2019-01-22 |
Simplified gate to source/drain region connections
Grant 10,181,522 - Neogi , et al. Ja | 2019-01-15 |
Simplified Gate To Source/drain Region Connections
App 20180240885 - Neogi; Tuhin Guha ; et al. | 2018-08-23 |
Fully Depleted Silicon-on-insulator (fdsoi) Transistor Device And Self-aligned Active Area In Fdsoi Bulk Exposed Regions
App 20180197882 - PRITCHARD; David ; et al. | 2018-07-12 |
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
Grant 9,941,301 - Pritchard , et al. April 10, 2 | 2018-04-10 |
CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer
Grant 9,373,548 - Pei , et al. June 21, 2 | 2016-06-21 |
SRAM cell with individual electrical device threshold control
Grant 9,048,136 - Mann , et al. June 2, 2 | 2015-06-02 |
SRAM cell with individual electrical device threshold control
Grant 9,029,956 - Mann , et al. May 12, 2 | 2015-05-12 |
Sram Cell With Individual Electrical Device Threshold Control
App 20130107610 - Mann; Randy W. ; et al. | 2013-05-02 |
Sram Cell With Individual Electrical Device Threshold Control
App 20130107608 - Mann; Randy W. ; et al. | 2013-05-02 |
Semiconductor device and method of manufacturing a semiconductor device
Grant 7,910,996 - Besser , et al. March 22, 2 | 2011-03-22 |
Semiconductor Device And Method Of Manufacturing A Semiconductor Device
App 20090267152 - Besser; Paul R. ; et al. | 2009-10-29 |
Integration Scheme For Constrained Seg Growth On Poly During Raised S/d Processing
App 20090236664 - Brown; David E. ; et al. | 2009-09-24 |
Semiconductor device and method of manufacturing a semiconductor device
Grant 7,572,705 - Besser , et al. August 11, 2 | 2009-08-11 |
Integration scheme for constrained SEG growth on poly during raised S/D processing
Grant 7,553,732 - Brown , et al. June 30, 2 | 2009-06-30 |
Stress Enhanced Cmos Circuits
App 20090008718 - PEI; Gen ; et al. | 2009-01-08 |
Stress enhanced CMOS circuits and methods for their fabrication
Grant 7,442,601 - Pei , et al. October 28, 2 | 2008-10-28 |
Method of forming a semiconductor device
Grant 7,402,485 - En , et al. July 22, 2 | 2008-07-22 |
Stress Enhanced Cmos Circuits And Methods For Their Fabrication
App 20080122002 - Pei; Gen ; et al. | 2008-05-29 |
Methods for post offset spacer clean for improved selective epitaxy silicon growth
Grant 7,241,700 - En , et al. July 10, 2 | 2007-07-10 |
Method of forming a semiconductor device having an epitaxial layer and device thereof
App 20060281271 - Brown; David E. ; et al. | 2006-12-14 |
Methodology for deposition of doped SEG for raised source/drain regions
App 20060252191 - Kammler; Thorsten ; et al. | 2006-11-09 |
Method of forming a gate electrode on a semiconductor device and a device incorporating same
Grant 7,087,509 - Roche , et al. August 8, 2 | 2006-08-08 |
Method of forming silicide layers over a plurality of semiconductor devices
Grant 6,787,464 - Cheek , et al. September 7, 2 | 2004-09-07 |
Maintaining LDD series resistance of MOS transistors by retarding dopant segregation
Grant 6,777,281 - Kadosh , et al. August 17, 2 | 2004-08-17 |
Semiconductor device and method for lowering miller capacitance for high-speed microprocessors
Grant 6,743,685 - Wu , et al. June 1, 2 | 2004-06-01 |
Channel isolation using dielectric isolation structures
Grant 6,727,558 - Duane , et al. April 27, 2 | 2004-04-27 |
Method of forming a hard mask for halo implants
Grant 6,624,035 - Luning , et al. September 23, 2 | 2003-09-23 |
Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors
Grant 6,617,219 - Duane , et al. September 9, 2 | 2003-09-09 |
Tilted counter-doped implant to sharpen halo profile
Grant 6,589,847 - Kadosh , et al. July 8, 2 | 2003-07-08 |
Removable spacer technique
Grant 6,506,642 - Luning , et al. January 14, 2 | 2003-01-14 |
Method of forming silicide contacts and device incorporation same
App 20020137268 - Pellerin, John G. ; et al. | 2002-09-26 |
Method for forming vertical profile of polysilicon gate electrodes
Grant 6,391,751 - Wu , et al. May 21, 2 | 2002-05-21 |
Angled halo implant tailoring using implant mask
Grant 6,372,587 - Cheek , et al. April 16, 2 | 2002-04-16 |
Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices
Grant 6,236,596 - Sobek , et al. May 22, 2 | 2001-05-22 |
Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing
Grant 6,168,637 - Randolph , et al. January 2, 2 | 2001-01-02 |
Subtractive dual damascene semiconductor device
Grant 6,051,882 - Avanzino , et al. April 18, 2 | 2000-04-18 |
Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
Grant 6,025,240 - Chan , et al. February 15, 2 | 2000-02-15 |
Method for obtaining a steep retrograde channel profile
Grant 5,989,963 - Luning , et al. November 23, 1 | 1999-11-23 |
Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration
Grant 5,888,867 - Wang , et al. March 30, 1 | 1999-03-30 |
Self aligned via dual damascene
Grant 5,795,823 - Avanzino , et al. August 18, 1 | 1998-08-18 |
Dual damascene with a sacrificial via fill
Grant 5,705,430 - Avanzino , et al. January 6, 1 | 1998-01-06 |
Subtractive dual damascene
Grant 5,691,238 - Avanzino , et al. November 25, 1 | 1997-11-25 |
Dual damascene with a protective mask for via etching
Grant 5,686,354 - Avanzino , et al. November 11, 1 | 1997-11-11 |
Self aligned via dual damascene
Grant 5,614,765 - Avanzino , et al. March 25, 1 | 1997-03-25 |
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