| Patent | Date |
|---|
Method and system for automated generation of masks for spacer formation from a desired final wafer pattern
Grant 9,274,410 - Lo , et al. March 1, 2 | 2016-03-01 |
Methods for optical proximity correction in the design and fabrication of integrated circuits
Grant 8,975,195 - Lukanc , et al. March 10, 2 | 2015-03-10 |
Methods For Optical Proximity Correction In The Design And Fabrication Of Integrated Circuits
App 20140220786 - Lukanc; Todd ; et al. | 2014-08-07 |
Method of forming an electronic device including forming features within a mask and a selective removal process
Grant 8,003,545 - Lukanc , et al. August 23, 2 | 2011-08-23 |
Method And System For Automated Generation Of Masks For Spacer Formation From A Desired Final Wafer Pattern
App 20110195348 - Lo; Wai ; et al. | 2011-08-11 |
Method Of Forming An Electronic Device Including Forming Features Within A Mask And A Selective Removal Process
App 20090209107 - Lukanc; Todd ; et al. | 2009-08-20 |
Method for increasing manufacturability of a circuit layout
Grant 7,487,492 - Singhal , et al. February 3, 2 | 2009-02-03 |
Method of strengthening photoresist to prevent pattern collapse
Grant 6,635,409 - Lyons , et al. October 21, 2 | 2003-10-21 |
Barrier layer integrity test
Grant 6,633,083 - Woo , et al. October 14, 2 | 2003-10-14 |
Variable design rule tool
Grant 6,516,450 - Hill , et al. February 4, 2 | 2003-02-04 |
Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers
Grant 6,479,350 - Ling , et al. November 12, 2 | 2002-11-12 |
Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers
Grant 6,472,317 - Wang , et al. October 29, 2 | 2002-10-29 |
Barrier layer integrity test
App 20020151093 - Woo, Christy Mei-Chu ; et al. | 2002-10-17 |
Two mask via pattern to improve pattern definition
App 20020106587 - Lukanc, Todd ; et al. | 2002-08-08 |
Phase shift mask and system and method for making the same
App 20020102471 - Lukanc, Todd | 2002-08-01 |
Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
Grant 6,312,874 - Chan , et al. November 6, 2 | 2001-11-06 |
Etch bias distribution across semiconductor wafer
App 20010031506 - Plat, Marina V. ; et al. | 2001-10-18 |
Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer
Grant 6,291,887 - Wang , et al. September 18, 2 | 2001-09-18 |
Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides
Grant 6,291,860 - Lukanc September 18, 2 | 2001-09-18 |
Use of an existing product map as a background for making test masks
Grant 6,279,147 - Buynoski , et al. August 21, 2 | 2001-08-21 |
Etch bias distribution across semiconductor wafer
Grant 6,262,435 - Plat , et al. July 17, 2 | 2001-07-17 |
Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers
Grant 6,255,735 - Wang , et al. July 3, 2 | 2001-07-03 |
Nitride disposable spacer to reduce mask count in CMOS transistor formation
Grant 6,218,224 - Lukanc , et al. April 17, 2 | 2001-04-17 |
Polishing pad and method for polishing porous materials
Grant 6,217,418 - Lukanc , et al. April 17, 2 | 2001-04-17 |
MOS transistor formation
Grant 6,184,114 - Lukanc February 6, 2 | 2001-02-06 |
Method of forming a dual damascene trench and borderless via structure
Grant 6,156,643 - Chan , et al. December 5, 2 | 2000-12-05 |
Nitride disposable spacer to reduce mask count in CMOS transistor formation
Grant 6,103,563 - Lukanc , et al. August 15, 2 | 2000-08-15 |
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