loadpatents
Patent applications and USPTO patent grants for Lucas; Gary J..The latest application filed is for "access unit and management segment memory operations".
Patent | Date |
---|---|
Access Unit And Management Segment Memory Operations App 20220222181 - McGlaughlin; Edward C. ;   et al. | 2022-07-14 |
Access unit and management segment memory operations Grant 11,301,391 - McGlaughlin , et al. April 12, 2 | 2022-04-12 |
Command Delay App 20210373887 - Dunlop; Bruce ;   et al. | 2021-12-02 |
Read Recovery Control Circuitry App 20210271548 - Wiita; Richard D. ;   et al. | 2021-09-02 |
Command delay Grant 11,093,244 - Dunlop , et al. August 17, 2 | 2021-08-17 |
Read recovery control circuitry Grant 11,023,317 - Wiita , et al. June 1, 2 | 2021-06-01 |
Command Tracking App 20210064368A1 - | 2021-03-04 |
Command Delay App 20210064369 - Dunlop; Bruce ;   et al. | 2021-03-04 |
Read Recovery Control Circuitry App 20210011804 - Wiita; Richard D. ;   et al. | 2021-01-14 |
Access Unit And Management Segment Memory Operations App 20200394140 - McGlaughlin; Edward C. ;   et al. | 2020-12-17 |
Access unit and management segment memory operations Grant 10,817,430 - McGlaughlin , et al. October 27, 2 | 2020-10-27 |
Access Unit And Management Segment Memory Operations App 20200104263 - McGlaughlin; Edward C. ;   et al. | 2020-04-02 |
System and method for detecting glitches on a high-speed interface Grant 7,827,455 - Eckel , et al. November 2, 2 | 2010-11-02 |
Controllable Interaction Between Multiple Event Monitoring Subsystems For Computing Environments App 20100162269 - Lucas; Gary J. ;   et al. | 2010-06-24 |
Early Response Indication for data retrieval in a multi-processor computing system App 20100131719 - Luba; Mark D. ;   et al. | 2010-05-27 |
Early response indication for data retrieval in a multi-processor computing system App 20090164689 - Luba; Mark D. ;   et al. | 2009-06-25 |
Pipeline controller for providing independent execution between the preliminary and advanced stages of a synchronous pipeline Grant 7,058,793 - Hartnett , et al. June 6, 2 | 2006-06-06 |
Method of and apparatus for saving time performing certain transfer instructions Grant 6,108,761 - Johnson , et al. August 22, 2 | 2000-08-22 |
Second level cache having instruction cache parity error control Grant 5,875,201 - Bauman , et al. February 23, 1 | 1999-02-23 |
Instruction flow control for an instruction processor Grant 5,867,699 - Kuslak , et al. February 2, 1 | 1999-02-02 |
Apparatus and method for processing a jump instruction preceded by a skip instruction Grant 5,644,759 - Lucas , et al. July 1, 1 | 1997-07-01 |
Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system Grant 5,408,629 - Tsuchiva , et al. April 18, 1 | 1995-04-18 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.