Lubeley; Dominik

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lubeley; Dominik.The latest application filed is for "method for dividing simulation models up between a processor and an fpga".

Company Profile

8.10.16

Lubeley; Dominik - Paderborn DE
Lubeley; Dominik - Verl DE
- Verl DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method For Dividing Simulation Models Up Between A Processor And An Fpga App 20220309218 - Lubeley; Dominik ; et al.	2022-09-29
Method for programming a programmable gate array in a distributed computer system Grant 11,442,884 - Agne , et al. September 13, 2	2022-09-13
Computer-implemented Method For Restructuring A Predefined Distributed Real-time Simulation Network App 20220060389 - KALTE; Heiko ; et al.	2022-02-24
Method, computer-based system and computer program product for planning partitions for a programmable gate array Grant 11,222,159 - Kalte , et al. January 11, 2	2022-01-11
Procedure for reviewing an FPGA-program Grant 11,187,748 - Kalte , et al. November 30, 2	2021-11-30
Method For Programming A Programmable Gate Array In A Distributed Computer System App 20210303501 - AGNE; Andreas ; et al.	2021-09-30
Method, Computer-based System And Computer Program Product For Planning Partitions For A Programmable Gate Array App 20210256190 - KALTE; Heiko ; et al.	2021-08-19
Method for troubleshooting the program logic of a system of distributed progammable gate arrays Grant 11,017,141 - Kalte , et al. May 25, 2	2021-05-25
Method For Troubleshooting The Program Logic Of A System Of Distributed Progammable Gate Arrays App 20200364392 - KALTE; Heiko ; et al.	2020-11-19
Incremental generation of an FPGA implementation with a graph-based similarity search Grant 10,706,196 - Lubeley , et al.	2020-07-07
Incremental generation of an FPGA implementation with a graph-based similarity search Grant 10671783 -	2020-06-02
Computer Network With A First And A Second Synchronizing Signal Transmitter App 20200145486 - AREND; Peter ; et al.	2020-05-07
Procedure For Reviewing An Fpga-program App 20200132766 - Kalte; Heiko ; et al.	2020-04-30
Method for creating an FPGA netlist Grant 10,394,989 - Kalte , et al. A	2019-08-27
Incremental Generation Of An Fpga Implementation With A Graph-based Similarity Search App 20190213294 - LUBELEY; Dominik ; et al.	2019-07-11
Method For Producing An Association List App 20190147129 - KALTE; Heiko ; et al.	2019-05-16
Method For Reading Out Variables From An Fpga App 20190138310 - Kalte; Heiko ; et al.	2019-05-09
Method for detecting the topology of electrical wiring Grant 10,224,930 - Lubeley , et al.	2019-03-05
Method For Detecting The Topology Of Electrical Wiring App 20180323784 - Lubeley; Dominik ; et al.	2018-11-08
Method for determining the power consumption of a programmable logic device Grant 10,102,325 - Lubeley , et al. October 16, 2	2018-10-16
Method for automatically generating a netlist of an FPGA program Grant 9,870,440 - Kalte , et al. January 16, 2	2018-01-16
Method For Creating An Fpga Netlist App 20170329877 - KALTE; Heiko ; et al.	2017-11-16
Method For Temporally Synchronizing The Output And/or Temporally Synchronizing The Processing Of Signals App 20170329732 - Kalte; Heiko ; et al.	2017-11-16
Method And Device For Accelerated Access To Signals Of A Programmable Logic Device App 20170126232 - KALTE; Heiko ; et al.	2017-05-04
Method For Determining The Power Consumption Of A Programmable Logic Device App 20170116363 - LUBELEY; Dominik ; et al.	2017-04-27
Method and device for accelerated access to signals of a programmable logic device Grant 9,628,085 - Kalte , et al. April 18, 2	2017-04-18
Method For Automatically Generating A Netlist Of An Fpga Program App 20150331983 - KALTE; Heiko ; et al.	2015-11-19

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