Lu; Sean Shau-Tu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lu; Sean Shau-Tu.The latest application filed is for "memory interface circuitry with improved timing margins".

Company Profile

1.16.1

Lu; Sean Shau-Tu - San Jose CA
- San Jose CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuitry and methods for measuring and correcting duty-cycle distortion Grant 9,818,471 - Oh , et al. November 14, 2	2017-11-14
Circuitry and methods for measuring and correcting duty-cycle distortion Grant 9,461,631 - Oh , et al. October 4, 2	2016-10-04
Integrated circuits having input-output circuits with dedicated memory controller circuitry Grant 9,330,218 - Chiu , et al. May 3, 2	2016-05-03
Memory interface circuitry with improved timing margins Grant 9,166,596 - Chong , et al. October 20, 2	2015-10-20
Circuit design technique for DQS enable/disable calibration Grant 9,158,873 - Chong , et al. October 13, 2	2015-10-13
Digital PVT compensation for delay chain Grant 9,059,716 - Nagarajan , et al. June 16, 2	2015-06-16
Methods and apparatus for clock tree phase alignment Grant 08922264 -	2014-12-30
Methods and apparatus for clock tree phase alignment Grant 8,922,264 - Chong , et al. December 30, 2	2014-12-30
Clock structure with calibration circuitry Grant 8,816,743 - Lu , et al. August 26, 2	2014-08-26
Circuit design technique for DQS enable/disable calibration Grant 8,787,097 - Chong , et al. July 22, 2	2014-07-22
Memory Interface Circuitry With Improved Timing Margins App 20140145756 - Chong; Yan ; et al.	2014-05-29
Digital PVT compensation for delay chain Grant 8,680,905 - Nagarajan , et al. March 25, 2	2014-03-25
Variation compensation circuitry for memory interface Grant 8,565,034 - Lu , et al. October 22, 2	2013-10-22
Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop Grant 8,237,475 - Nagarajan , et al. August 7, 2	2012-08-07
Digitally controlled delay-locked loops Grant 7,746,134 - Lu , et al. June 29, 2	2010-06-29

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