Lu; Darsen D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lu; Darsen D..The latest application filed is for "distributed decoupling capacitor".

Company Profile

14.35.31

Lu; Darsen D. - Taichung TW
Lu; Darsen D. - Mount Kisco NY
Lu; Darsen D. - Westchester NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Distributed decoupling capacitor Grant 10,903,208 - Cheng , et al. January 26, 2	2021-01-26
Dielectric isolated fin with improved fin profile Grant 10,892,364 - Cheng , et al. January 12, 2	2021-01-12
Semiconductor structures having increased channel strain using fin release in gate regions Grant 10,886,385 - Cheng , et al. January 5, 2	2021-01-05
FinFET with reduced parasitic capacitance Grant 10,734,477 - Cheng , et al.	2020-08-04
Distributed Decoupling Capacitor App 20200152622 - Cheng; Kangguo ; et al.	2020-05-14
Distributed decoupling capacitor Grant 10,593,663 - Cheng , et al.	2020-03-17
Dielectric Isolated Fin With Improved Fin Profile App 20200083374 - Cheng; Kangguo ; et al.	2020-03-12
Dielectric isolated fin with improved fin profile Grant 10,546,955 - Cheng , et al. Ja	2020-01-28
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions App 20190237561 - Cheng; Kangguo ; et al.	2019-08-01
Semiconductor structures having increased channel strain using fin release in gate regions Grant 10,347,752 - Cheng , et al. July 9, 2	2019-07-09
Finfet With Reduced Parasitic Capacitance App 20190165095 - Cheng; Kangguo ; et al.	2019-05-30
Distributed decoupling capacitor Grant 10,262,991 - Cheng , et al.	2019-04-16
FinFET with reduced parasitic capacitance Grant 10,243,042 - Cheng , et al.	2019-03-26
FinFET with reduced parasitic capacitance Grant 10,177,223 - Cheng , et al. J	2019-01-08
P-FET with graded silicon-germanium channel Grant 10,153,157 - Cheng , et al. Dec	2018-12-11
Semiconductor structures having increased channel strain using fin release in gate regions Grant 10,056,474 - Cheng , et al. August 21, 2	2018-08-21
Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices Grant 9,997,540 - Cheng , et al. June 12, 2	2018-06-12
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions App 20180130894 - CHENG; Kangguo ; et al.	2018-05-10
Strain release in pFET regions Grant 9,966,387 - Cheng , et al. May 8, 2	2018-05-08
Dielectric Isolated Fin With Improved Fin Profile App 20180122944 - Cheng; Kangguo ; et al.	2018-05-03
Semiconductor structures having increased channel strain using fin release in gate regions Grant 9,954,083 - Cheng , et al. April 24, 2	2018-04-24
Dielectric isolated fin with improved fin profile Grant 9,917,188 - Cheng , et al. March 13, 2	2018-03-13
Finfet With Reduced Parasitic Capacitance App 20170365658 - Cheng; Kangguo ; et al.	2017-12-21
Finfet With Reduced Parasitic Capacitance App 20170365659 - Cheng; Kangguo ; et al.	2017-12-21
FinFET PCM access transistor having gate-wrapped source and drain regions Grant 9,825,094 - Lam , et al. November 21, 2	2017-11-21
FinFET PCM access transistor having gate-wrapped source and drain regions Grant 9,825,093 - Lam , et al. November 21, 2	2017-11-21
FinFET with reduced parasitic capacitance Grant 9,786,737 - Cheng , et al. October 10, 2	2017-10-10
Strain release in PFET regions Grant 9,761,610 - Cheng , et al. September 12, 2	2017-09-12
Finfet With Reduced Parasitic Capacitance App 20170162650 - Cheng; Kangguo ; et al.	2017-06-08
Structure and method to make strained FinFET with improved junction capacitance and low leakage Grant 9,653,541 - Cheng , et al. May 16, 2	2017-05-16
STRUCTURE AND METHOD FOR COMPRESSIVELY STRAINED SILICON GERMANIUM FINS FOR pFET DEVICES AND TENSILY STRAINED SILICON FINS FOR nFET DEVICES App 20170125447 - Cheng; Kangguo ; et al.	2017-05-04
Asymmetric finFET memory access transistor Grant 9,583,624 - Lam , et al. February 28, 2	2017-02-28
Structure and method for advanced bulk fin isolation Grant 9,583,492 - Cheng , et al. February 28, 2	2017-02-28
Strain Release In Pfet Regions App 20170053943 - Cheng; Kangguo ; et al.	2017-02-23
Finfet Pcm Access Transistor Having Gate-wrapped Source And Drain Regions App 20170053966 - Lam; Chung H. ; et al.	2017-02-23
Finfet Pcm Access Transistor Having Gate-wrapped Source And Drain Regions App 20170054005 - Lam; Chung H. ; et al.	2017-02-23
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions App 20170053994 - Cheng; Kangguo ; et al.	2017-02-23
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions App 20170053839 - Cheng; Kangguo ; et al.	2017-02-23
Dielectric Isolated Fin With Improved Fin Profile App 20170040452 - Cheng; Kangguo ; et al.	2017-02-09
Structure and method for advanced bulk fin isolation Grant 9,564,439 - Cheng , et al. February 7, 2	2017-02-07
Asymmetric finFET memory access transistor Grant 9,553,173 - Lam , et al. January 24, 2	2017-01-24
Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices Grant 9,548,386 - Cheng , et al. January 17, 2	2017-01-17
Dielectric isolated fin with improved fin profile Grant 9,548,213 - Cheng , et al. January 17, 2	2017-01-17
Strain release in PFET regions Grant 9,543,323 - Cheng , et al. January 10, 2	2017-01-10
Distributed Decoupling Capacitor App 20170005088 - Cheng; Kangguo ; et al.	2017-01-05
Distributed Decoupling Capacitor App 20170005087 - Cheng; Kangguo ; et al.	2017-01-05
Lateral bipolar junction transistor having graded SiGe base Grant 9,525,027 - Hashemi , et al. December 20, 2	2016-12-20
Strain Release In Pfet Regions App 20160359003 - Cheng; Kangguo ; et al.	2016-12-08
Radiation tolerant device structure Grant 9,515,171 - Doris , et al. December 6, 2	2016-12-06
Distributed decoupling capacitor Grant 9,455,250 - Cheng , et al. September 27, 2	2016-09-27
Dielectric Isolated Fin With Improved Fin Profile App 20160233315 - Cheng; Kangguo ; et al.	2016-08-11
Strain Release In Pfet Regions App 20160204131 - Cheng; Kangguo ; et al.	2016-07-14
Structure And Method For Advanced Bulk Fin Isolation App 20160197078 - Cheng; Kangguo ; et al.	2016-07-07
Structure And Method For Advanced Bulk Fin Isolation App 20160197077 - Cheng; Kangguo ; et al.	2016-07-07
Semiconductor device including dielectrically isolated finFETs and buried stressor Grant 9,362,400 - Cheng , et al. June 7, 2	2016-06-07
Structure And Method To Make Strained Finfet With Improved Junction Capacitance And Low Leakage App 20160133697 - Cheng; Kangguo ; et al.	2016-05-12
Structure and method for advanced bulk fin isolation Grant 9,299,618 - Cheng , et al. March 29, 2	2016-03-29
Structure And Method For Advanced Bulk Fin Isolation App 20160086858 - Cheng; Kangguo ; et al.	2016-03-24
P-fet With Graded Silicon-germanium Channel App 20160064210 - Cheng; Kangguo ; et al.	2016-03-03
Structure and method to make strained FinFET with improved junction capacitance and low leakage Grant 9,276,113 - Cheng , et al. March 1, 2	2016-03-01
P-fet With Graded Silicon-germanium Channel App 20150364555 - Cheng; Kangguo ; et al.	2015-12-17
Engineered substrate and device for co-integration of strained silicon and relaxed silicon Grant 9,209,065 - Cheng , et al. December 8, 2	2015-12-08
P-fet With Graded Silicon-germanium Channel App 20150270344 - Cheng; Kangguo ; et al.	2015-09-24
LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING GRADED SiGe BASE App 20150263091 - Hashemi; Pouya ; et al.	2015-09-17
Structure And Method To Make Strained Finfet With Improved Junction Capacitance And Low Leakage App 20150255606 - Cheng; Kangguo ; et al.	2015-09-10
Dielectric Isolated Fin With Improved Fin Profile App 20150243755 - Cheng; Kangguo ; et al.	2015-08-27