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Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment
Grant 9,460,258 - Peart , et al. October 4, 2 | 2016-10-04 |
Shaping Integrated With Power Network Synthesis (pns) For Power Grid (pg) Alignment
App 20140181773 - Peart; David L. ; et al. | 2014-06-26 |
Method and computer program for generating grounded shielding wires for signal wiring
Grant 8,516,425 - Nikitin , et al. August 20, 2 | 2013-08-20 |
Signal Delay Skew Reduction System
App 20120278783 - Nikitin; Andrey ; et al. | 2012-11-01 |
Method and apparatus for balancing signal delay skew
Grant 8,239,813 - Nikitin , et al. August 7, 2 | 2012-08-07 |
Signal Delay Skew Reduction System
App 20110258587 - Nikitin; Andrey ; et al. | 2011-10-20 |
Signal delay skew reduction system
Grant 7,996,804 - Nikitin , et al. August 9, 2 | 2011-08-09 |
Signal Delay Skew Reduction System
App 20090187873 - Nikitin; Andrey ; et al. | 2009-07-23 |
Optimizing IC clock structures by minimizing clock uncertainty
Grant 7,356,785 - Lu , et al. April 8, 2 | 2008-04-08 |
Method of buffer insertion to achieve pin specific delays
Grant 7,243,324 - Lu , et al. July 10, 2 | 2007-07-10 |
Optimizing IC clock structures by minimizing clock uncertainty
App 20060190886 - Lu; Aiguo ; et al. | 2006-08-24 |
Method of buffer insertion to achieve pin specific delays
App 20060190901 - Lu; Aiguo ; et al. | 2006-08-24 |
Optimizing IC clock structures by minimizing clock uncertainty
Grant 7,096,442 - Lu , et al. August 22, 2 | 2006-08-22 |
Optimization of adder based circuit architecture
Grant 6,934,733 - Gashkov , et al. August 23, 2 | 2005-08-23 |
Method to find boolean function symmetries
Grant 6,868,536 - Gasanov , et al. March 15, 2 | 2005-03-15 |
Optimizing IC clock structures by minimizing clock uncertainty
App 20050010884 - Lu, Aiguo ; et al. | 2005-01-13 |
Process of restructuring logics in ICs for setup and hold time optimization
Grant 6,810,515 - Lu , et al. October 26, 2 | 2004-10-26 |
Method to find boolean function symmetries
App 20040098676 - Gasanov, Elyar E. ; et al. | 2004-05-20 |
Process of restructuring logics in ICs for setup and hold time optimization
App 20040060012 - Lu, Aiguo ; et al. | 2004-03-25 |
Floor plan tester for integrated circuit design
Grant 6,701,493 - Gasanov , et al. March 2, 2 | 2004-03-02 |
Optimization of comparator architecture
Grant 6,691,283 - Gashkov , et al. February 10, 2 | 2004-02-10 |
Assignment of cell coordinates
Grant 6,637,016 - Gasanov , et al. October 21, 2 | 2003-10-21 |
Floor plan tester for integrated circuit design
App 20030188274 - Gasanov, Elyar E. ; et al. | 2003-10-02 |
Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells
Grant 6,629,304 - Gasanov , et al. September 30, 2 | 2003-09-30 |
Netlist resynthesis program based on physical delay calculation
Grant 6,557,144 - Lu , et al. April 29, 2 | 2003-04-29 |
Timing recomputation
Grant 6,553,551 - Zolotykh , et al. April 22, 2 | 2003-04-22 |
Method in integrating clock tree synthesis and timing optimization for an integrated circuit design
Grant 6,550,044 - Pavisic , et al. April 15, 2 | 2003-04-15 |
Changing clock delays in an integrated circuit for skew optimization
Grant 6,550,045 - Lu , et al. April 15, 2 | 2003-04-15 |
Parallelization Of Resynthesis
App 20020162085 - Zolotykh, Andrej A. ; et al. | 2002-10-31 |
Parallelization of resynthesis
Grant 6,470,487 - Zolotykh , et al. October 22, 2 | 2002-10-22 |
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