Low; Chun Hui

Patent Applications and Registrations

Patent applications and USPTO patent grants for Low; Chun Hui.The latest application filed is for "via electromigration improvement by changing the via bottom geometric profile".

Company Profile

0.12.7

Low; Chun Hui - Singapore N/A SG
Low; Chun Hui - Johor MY
Low; Chun Hui - Batu Pahat Johor
Low; Chun Hui - Misia MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming high-k dielectric stop layer for contact hole opening Grant 8,354,347 - Ye , et al. January 15, 2	2013-01-15
Critical dimension for trench and vias Grant 8,293,545 - Cong , et al. October 23, 2	2012-10-23
Via electromigration improvement by changing the via bottom geometric profile Grant 7,781,895 - Zhang , et al. August 24, 2	2010-08-24
Via electromigration improvement by changing the via bottom geometric profile Grant 7,691,739 - Zhang , et al. April 6, 2	2010-04-06
Via Electromigration Improvement By Changing The Via Bottom Geometric Profile App 20090250818 - Zhang; Bei Chao ; et al.	2009-10-08
Method of forming high-k dielectric stop layer for contact hole opening App 20090146296 - YE; Jianhui ; et al.	2009-06-11
Critical Dimension For Trench And Vias App 20090108257 - Cong; Hai ; et al.	2009-04-30
Multiple layer resist scheme implementing etch recipe particular to each layer Grant 7,352,064 - Fuller , et al. April 1, 2	2008-04-01
Via electromigration improvement by changing the via bottom geometric profile App 20060160354 - Zhang; BeiChao ; et al.	2006-07-20
Via electromigration improvement by changing the via bottom geometric profile Grant 7,045,455 - Zhang , et al. May 16, 2	2006-05-16
Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer App 20060094230 - Fuller; Nicholas C.M. ; et al.	2006-05-04
Via electromigration improvement by changing the via bottom geometric profile App 20050090097 - Zhang, Beichao ; et al.	2005-04-28
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts Grant 6,350,661 - Lim , et al. February 26, 2	2002-02-26
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts App 20010031540 - Lim, Chong Wee ; et al.	2001-10-18
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts Grant 6,297,126 - Lim , et al. October 2, 2	2001-10-02
Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication Grant 6,271,133 - Lim , et al. August 7, 2	2001-08-07
Partially recessed shallow trench isolation method for fabricating borderless contacts Grant 6,265,302 - Lim , et al. July 24, 2	2001-07-24
Method to form shallow trench isolations with rounded corners and reduced trench oxide recess Grant 6,228,727 - Lim , et al. May 8, 2	2001-05-08

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