Lotz; Jonathan P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lotz; Jonathan P..The latest application filed is for "backside power delivery using die stacking".

Company Profile

0.11.13

Lotz; Jonathan P. - Fort Collins CO
Lotz; Jonathan P. - Ft. Collins CO
Lotz; Jonathan P - Fort Collins CO
Lotz; Jonathan P - Ft Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Backside Power Delivery Using Die Stacking App 20120292777 - Lotz; Jonathan P.	2012-11-22
Array-based memory abstraction App 20070261059 - Orth; Joseph F. ; et al.	2007-11-08
Triple redundant latch design with low delay time Grant 7,215,581 - Lotz , et al. May 8, 2	2007-05-08
High reliability triple redundant latch with voting logic on each storage node Grant 7,179,690 - Lotz , et al. February 20, 2	2007-02-20
High reliability triple redundant latch with integrated testability Grant 7,095,262 - Petersen , et al. August 22, 2	2006-08-22
High reliability memory element with improved delay time Grant 7,054,203 - Lotz , et al. May 30, 2	2006-05-30
High reliability triple redundant memory element with integrated testability and voting structures on each latch Grant 7,027,333 - Petersen , et al. April 11, 2	2006-04-11
High reliability triple redundant memory element with integrated testability and voting structures on each latch App 20060050550 - Petersen; John T. ; et al.	2006-03-09
High reliability triple redundant latch with integrated testability App 20060012413 - Petersen; John T. ; et al.	2006-01-19
High reliability triple redundant latch with voting logic on each storage node App 20050265089 - Lotz, Jonathan P. ; et al.	2005-12-01
Triple redundant latch design with low delay time App 20050251729 - Lotz, Jonathan P. ; et al.	2005-11-10
High reliability memory element with improved delay time App 20050242828 - Lotz, Jonathan P. ; et al.	2005-11-03
High reliability triple redundant latch with voting logic on each storage node Grant 6,937,527 - Lotz , et al. August 30, 2	2005-08-30
Triple redundant latch design with storage node recovery Grant 6,930,527 - Cabanas-Holmen , et al. August 16, 2	2005-08-16
Triple Redundant Latch Design With Storage Node Recovery App 20050168257 - Cabanas-Holmen, Manuel ; et al.	2005-08-04
Method for creating a useful bipolar junction transistor from a parasitic bipolar junction transistor on a MOSFET Grant 6,624,482 - Lotz September 23, 2	2003-09-23
Identification of stale entries in a computer cache App 20030084253 - Johnson, David J.C. ; et al.	2003-05-01
Preemptive eviction of stale entries is a computer cache by use of age-bits App 20030084249 - Johnson, David J.C. ; et al.	2003-05-01
Hierarchical metal one usage tool for child level leaf cell App 20020157064 - Maroni, Peter D. ; et al.	2002-10-24
System and method for improving performance of dynamic circuits App 20020149393 - Coppin, Justin Allan ; et al.	2002-10-17
Method for creating a useful bipolar junction transistor from a parasitic bipolar junction transistor on a MOSFET App 20020146880 - Lotz, Jonathan P.	2002-10-10
System and method for on-chip debug support and performance monitoring in a microprocessor Grant 5,867,644 - Ranson , et al. February 2, 1	1999-02-02
Method and system for recovering from cache misses Grant 5,784,587 - Lotz , et al. July 21, 1	1998-07-21
Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words Grant 5,748,934 - Lesartre , et al. May 5, 1	1998-05-05

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