| Patent | Date |
|---|
Method and apparatus for efficient, low-latency, streaming memory copies
Grant 8,880,829 - Reid , et al. November 4, 2 | 2014-11-04 |
Method And Apparatus For Efficient, Low-latency, Streaming Memory Copies
App 20140143513 - Reid; Gregory A. ; et al. | 2014-05-22 |
Cooperative writes over the address channel of a bus
Grant 8,675,679 - Hofmann , et al. March 18, 2 | 2014-03-18 |
Accelerated Interleaved Memory Data Transfers In Microprocessor-based Systems, And Related Devices, Methods, And Computer-readable Media
App 20130232304 - Lohman; Terence J. ; et al. | 2013-09-05 |
Auxiliary writes over address channel
Grant 8,521,914 - Hofmann , et al. August 27, 2 | 2013-08-27 |
Auxiliary Writes Over Address Channel
App 20120096202 - Hofmann; Richard Gerard ; et al. | 2012-04-19 |
Cooperative Writes over the Address Channel of a Bus
App 20120096201 - Hofmann; Richard Gerard ; et al. | 2012-04-19 |
Cooperative writes over the address channel of a bus
Grant 8,107,492 - Hofmann , et al. January 31, 2 | 2012-01-31 |
Auxiliary writes over address channel
Grant 8,108,563 - Hofmann , et al. January 31, 2 | 2012-01-31 |
Single bus command having transfer information for transferring data in a processing system
Grant 7,822,903 - Hofmann , et al. October 26, 2 | 2010-10-26 |
Auxiliary Writes Over Address Channel
App 20070233904 - Hofmann; Richard Gerard ; et al. | 2007-10-04 |
Single Bus Command for Transferring Data in a Processing System
App 20070204091 - Hofmann; Richard Gerard ; et al. | 2007-08-30 |
Cooperative Writes Over the Address Channel of a Bus
App 20070201506 - Hofmann; Richard Gerard ; et al. | 2007-08-30 |
Bus access arbitration scheme
Grant 7,249,210 - Ganasan , et al. July 24, 2 | 2007-07-24 |
Bus access arbitration scheme
App 20060200607 - Subramaniam Ganasan; Jaya Prakash ; et al. | 2006-09-07 |
Method and apparatus for arbitrating for a bus to enable split transaction bus protocols
Grant 5,621,897 - Boury , et al. April 15, 1 | 1997-04-15 |
Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components
Grant 5,615,217 - Horne , et al. March 25, 1 | 1997-03-25 |
Expandable high performance FIFO design which includes memory cells having respective cell multiplexors
Grant 5,551,009 - Amini , et al. August 27, 1 | 1996-08-27 |
Dynamic bus sizing of DMA transfers
Grant 5,548,786 - Amini , et al. August 20, 1 | 1996-08-20 |
System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus
Grant 5,544,346 - Amini , et al. August 6, 1 | 1996-08-06 |
System direct memory access (DMA) support logic for PCI based computer system
Grant 5,450,551 - Amini , et al. September 12, 1 | 1995-09-12 |
Arbitration logic for multiple bus computer system
Grant 5,396,602 - Amini , et al. March 7, 1 | 1995-03-07 |
DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
Grant 5,381,538 - Amini , et al. January 10, 1 | 1995-01-10 |
Error detection and recovery in a DMA controller
Grant 5,333,274 - Amini , et al. July 26, 1 | 1994-07-26 |
Controlling bus allocation using arbitration hold
Grant 5,301,282 - Amini , et al. April 5, 1 | 1994-04-05 |
Arbitration control logic for computer system having dual bus architecture
Grant 5,265,211 - Amini , et al. November 23, 1 | 1993-11-23 |
Bus interface logic for computer system having dual bus architecture
Grant 5,255,374 - Aldereguia , et al. October 19, 1 | 1993-10-19 |
CPU bus allocation control
Grant 5,239,631 - Boury , et al. August 24, 1 | 1993-08-24 |
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