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Patent applications and USPTO patent grants for Loh; Siang Poh.The latest application filed is for "3d built-in self-test scheme for 3d assembly defect detection".
Patent | Date |
---|---|
Multi-layer distributed network Grant 9,430,433 - Oh , et al. August 30, 2 | 2016-08-30 |
Stacked integrated circuit with redundancy in die-to-die interconnects Grant 9,236,864 - Loh , et al. January 12, 2 | 2016-01-12 |
3D built-in self-test scheme for 3D assembly defect detection Grant 8,793,547 - Loh , et al. July 29, 2 | 2014-07-29 |
Method and apparatus for providing signal routing control Grant 8,786,308 - Loh , et al. July 22, 2 | 2014-07-22 |
3d Built-in Self-test Scheme For 3d Assembly Defect Detection App 20140189456 - Loh; Siang Poh ;   et al. | 2014-07-03 |
Multi-layer distributed network Grant 8,166,429 - Oh , et al. April 24, 2 | 2012-04-24 |
Periphery clock signal distribution circuitry for structured ASIC devices Grant 7,622,952 - Lim , et al. November 24, 2 | 2009-11-24 |
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