Lo; Wai

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lo; Wai.The latest application filed is for "metal-insualtor-metal (mim) device and method of formation thererof".

Company Profile

0.34.25

Lo; Wai - Palo Alto CA US
Lo; Wai - Richmond Hill CA
Lo; Wai - Lake Oswego OR US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for automated generation of masks for spacer formation from a desired final wafer pattern Grant 9,274,410 - Lo , et al. March 1, 2	2016-03-01
Defect mitigation structures for semiconductor devices Grant 9,105,469 - Patel , et al. August 11, 2	2015-08-11
Metal-insualtor-metal (MIM) device and method of formation thereof Grant 9,012,299 - Avanzino , et al. April 21, 2	2015-04-21
Metal-insualtor-metal (mim) Device And Method Of Formation Thererof App 20140357044 - AVANZINO; Steven ; et al.	2014-12-04
Metal-insulator-metal (MIM) device and method of formation thereof Grant 8,828,837 - Avanzino , et al. September 9, 2	2014-09-09
Metal-insulator-metal (mim) Device And Method Of Formation Thereof App 20130237030 - AVANZINO; Steven ; et al.	2013-09-12
Video Player With Multiple Grpahics Processors App 20130148947 - Glen; David I.J. ; et al.	2013-06-13
Metal-insulator-metal (MIM) device and method of formation thereof Grant 8,445,913 - Avanzino , et al. May 21, 2	2013-05-21
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Grant 8,384,165 - Carter , et al. February 26, 2	2013-02-26
Methods for forming a memory cell having a top oxide spacer Grant 8,384,146 - Fang , et al. February 26, 2	2013-02-26
Defect Mitigation Structures For Semiconductor Devices App 20130001641 - Patel; Zubin P. ; et al.	2013-01-03
Methods For Forming A Memory Cell Having A Top Oxide Spacer App 20120181601 - FANG; Shenqing ; et al.	2012-07-19
Methods for forming a memory cell having a top oxide spacer Grant 8,202,779 - Fang , et al. June 19, 2	2012-06-19
Methods For Forming A Memory Cell Having A Top Oxide Spacer App 20110233647 - FANG; Shenqing ; et al.	2011-09-29
Method And System For Automated Generation Of Masks For Spacer Formation From A Desired Final Wafer Pattern App 20110195348 - Lo; Wai ; et al.	2011-08-11
Bi-axial texturing of high-K dielectric films to reduce leakage currents Grant 7,956,401 - Lo , et al. June 7, 2	2011-06-07
Pin diode device and architecture Grant 7,916,529 - Lo , et al. March 29, 2	2011-03-29
Split charge storage node inner spacer process Grant 7,829,936 - Shen , et al. November 9, 2	2010-11-09
Triple poly-si replacement scheme for memory devices Grant 7,807,580 - Lee , et al. October 5, 2	2010-10-05
Pin Diode Device And Architecture App 20100208517 - Lo; Wai ; et al.	2010-08-19
Bi-axial Texturing Of High-k Dielectric Films To Reduce Leakage Currents App 20100022060 - LO; Wai ; et al.	2010-01-28
Bi-axial texturing of high-K dielectric films to reduce leakage currents Grant 7,619,272 - Lo , et al. November 17, 2	2009-11-17
Process and apparatus for simultaneous light and radical surface treatment of integrated circuit structure Grant 7,553,772 - Gu , et al. June 30, 2	2009-06-30
Metal-insulator-metal (MIM) device and method of formation thereof App 20090109598 - Avanzino; Steven ; et al.	2009-04-30
Split Charge Storage Node Inner Spacer Process App 20090101963 - Shen; Minghao ; et al.	2009-04-23
Application Of Gate Edge Liner To Maintain Gate Length Cd In A Replacement Gate Transistor Flow App 20080308882 - Carter; Richard J. ; et al.	2008-12-18
Triple Poly-si Replacement Scheme For Memory Devices App 20080268650 - Lee; Chungho ; et al.	2008-10-30
High k gate insulator removal Grant 7,413,996 - Kamath , et al. August 19, 2	2008-08-19
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Grant 7,405,116 - Carter , et al. July 29, 2	2008-07-29
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL App 20080150090 - Lin; Hong ; et al.	2008-06-26
Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1-xGe.sub.x as sacrificial material Grant 7,365,015 - Lin , et al. April 29, 2	2008-04-29
Superconductor wires for back end interconnects Grant 7,341,978 - Gu , et al. March 11, 2	2008-03-11
Incorporating dopants to enhance the dielectric properties of metal silicates Grant 7,312,127 - Lo , et al. December 25, 2	2007-12-25
Interconnect dielectric tuning Grant 7,259,462 - Lo , et al. August 21, 2	2007-08-21
Implantable, fully integrated and high performance semiconductor device for retinal prostheses App 20070005116 - Lo; Wai	2007-01-04
High resolution semiconductor bio-chip with configuration sensing flexibility App 20060252143 - Lo; Wai	2006-11-09
Superconductor wires for back end interconnects App 20060197193 - Gu; Shiqun ; et al.	2006-09-07
Incorporating dopants to enhance the dielectric properties of metal silicates App 20060166496 - Lo; Wai ; et al.	2006-07-27
Interconnect dielectric tuning Grant 7,081,406 - Lo , et al. July 25, 2	2006-07-25
Incorporating dopants to enhance the dielectric properties of metal silicates Grant 7,064,062 - Lo , et al. June 20, 2	2006-06-20
Bi-axial texturing of high-K dielectric films to reduce leakage currents App 20060118919 - Lo; Wai ; et al.	2006-06-08
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow App 20060035425 - Carter; Richard J. ; et al.	2006-02-16
Interconnect dielectric tuning App 20060035455 - Lo; Wai ; et al.	2006-02-16
Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material App 20060011994 - Lin; Hong ; et al.	2006-01-19
Incorporating dopants to enhance the dielectric properties of metal silicates App 20050127458 - Lo, Wai ; et al.	2005-06-16
Plasma removal of high k metal oxide App 20050064716 - Lin, Hong ; et al.	2005-03-24
Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams Grant 6,864,141 - Lo , et al. March 8, 2	2005-03-08
Thin gate dielectric for a CMOS transistor and method of fabrication thereof Grant 6,849,512 - Lo , et al. February 1, 2	2005-02-01
Thin film CMOS calibration standard having protective cover layer Grant 6,830,943 - Lo , et al. December 14, 2	2004-12-14
Selective high k dielectrics removal Grant 6,818,516 - Lo , et al. November 16, 2	2004-11-16
High k gate insulator removal App 20040203246 - Kamath, Arvind ; et al.	2004-10-14
High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation Grant 6,746,925 - Lin , et al. June 8, 2	2004-06-08
Thin film CMOS calibration standard having protective cover layer Grant 6,674,092 - Lo , et al. January 6, 2	2004-01-06
Method and apparatus for processing video signals having associated access restriction data Grant 6,606,450 - Klebanoy , et al. August 12, 2	2003-08-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.