Lo; Hsien-Ching

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lo; Hsien-Ching.The latest application filed is for "single diffusion break device for fdsoi".

Company Profile

31.35.27

Lo; Hsien-Ching - Clifton Park NY
Lo; Hsien-Ching - Round Rock TX
Lo; Hsien-Ching - Guilderland NY
Lo; Hsien-Ching - Taoyuan N/A TW
LO; Hsien-Ching - Taoyuan City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Single diffusion break device for FDSOI Grant 10,957,578 - Hong , et al. March 23, 2	2021-03-23
Etch stop layer for use in forming contacts that extend to multiple depths Grant 10,714,577 - Hong , et al.	2020-07-14
FinFET device with a wrap-around silicide source/drain contact structure Grant 10,700,173 - Qi , et al.	2020-06-30
Fin-type transistors with spacers on the gates Grant 10,636,894 - Shen , et al.	2020-04-28
Etch Stop Layer For Use In Forming Contacts That Extend To Multiple Depths App 20200105886 - Hong; Wei ; et al.	2020-04-02
Single Diffusion Break Device For Fdsoi App 20200105584 - HONG; Wei ; et al.	2020-04-02
Finfets Having Gates Parallel To Fins App 20200066883 - Shen; Yanping ; et al.	2020-02-27
Wrap-all-around contact for nanosheet-FET and method of forming same Grant 10,559,656 - Bourjot , et al. Feb	2020-02-11
Field-effect Transistors With Improved Dielectric Gap Fill App 20200043779 - Hong; Wei ; et al.	2020-02-06
FinFETs having gates parallel to fins Grant 10,553,707 - Shen , et al. Fe	2020-02-04
Field-effect transistors with improved dielectric gap fill Grant 10,546,775 - Hong , et al. Ja	2020-01-28
Composite Spacers For Tailoring The Shape Of The Source And Drain Regions Of A Field-effect Transistor App 20200020770 - Qi; Yi ; et al.	2020-01-16
Wrap-all-around Contact For Nanosheet-fet And Method Of Forming Same App 20190341448 - Bourjot; Emilie M.S. ; et al.	2019-11-07
Epitaxial region for embedded source/drain region having uniform thickness Grant 10,461,155 - Yong , et al. Oc	2019-10-29
Finfet Device With A Wrap-around Silicide Source/drain Contact Structure App 20190312117 - Qi; Yi ; et al.	2019-10-10
Multiple-layer spacers for field-effect transistors Grant 10,431,665 - Han , et al. O	2019-10-01
Fin-type Transistors With Spacers On The Gates App 20190280105 - Shen; Yanping ; et al.	2019-09-12
Multiple gate length device with self-aligned top junction Grant 10,410,929 - Zang , et al. Sept	2019-09-10
Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same Grant 10,388,652 - Shi , et al. A	2019-08-20
Single-curvature cavity for semiconductor epitaxy Grant 10,355,104 - Qi , et al. July 16, 2	2019-07-16
Multiple Gate Length Device With Self-aligned Top Junction App 20190206743 - ZANG; Hui ; et al.	2019-07-04
Dual-curvature Cavity For Epitaxial Semiconductor Growth App 20190181243 - Vinslava; Alina ; et al.	2019-06-13
Dual-curvature cavity for epitaxial semiconductor growth Grant 10,297,675 - Vinslava , et al.	2019-05-21
Epitaxial Region For Embedded Source/drain Region Having Uniform Thickness App 20190148492 - Yong; Yoong Hooi ; et al.	2019-05-16
Integrated Circuit Structure Including Single Diffusion Break Abutting End Isolation Region, And Methods Of Forming Same App 20190148373 - Shi; Yongiun ; et al.	2019-05-16
Dual-curvature Cavity For Epitaxial Semiconductor Growth App 20190131433 - Vinslava; Alina ; et al.	2019-05-02
Single-curvature Cavity For Semiconductor Epitaxy App 20190131432 - Qi; Yi ; et al.	2019-05-02
Method of forming a vertical field effect transistor (VFET) and a VFET structure Grant 10,276,689 - Qi , et al.	2019-04-30
Boundary spacer structure and integration Grant 10,262,903 - Holt , et al.	2019-04-16
Method Of Forming Vertical Field Effect Transistors With Different Gate Lengths And A Resulting Structure App 20190103319 - Qi; Yi ; et al.	2019-04-04
Method of forming vertical field effect transistors with different gate lengths and a resulting structure Grant 10,249,538 - Qi , et al.	2019-04-02
Vertical-transport field-effect transistors with an etched-through source/drain cavity Grant 10,211,317 - Qi , et al. Feb	2019-02-19
Vertical-transport Field-effect Transistors With An Etched-through Source/drain Cavity App 20190051735 - Qi; Yi ; et al.	2019-02-14
Boundary Spacer Structure And Integration App 20180374759 - HOLT; Judson R. ; et al.	2018-12-27
Finfet diffusion break having protective liner in fin insulator Grant 10,164,010 - Hong , et al. Dec	2018-12-25
Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method Grant 10,163,635 - Qi , et al. Dec	2018-12-25
Method Of Forming A Vertical Field Effect Transistor (vfet) And A Vfet Structure App 20180358452 - QI; YI ; et al.	2018-12-13
Methods Of Forming Epi Semiconductor Material On A Thinned Fin In The Source/drain Regions Of A Finfet Device App 20180323269 - Qi; Yi ; et al.	2018-11-08
Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device Grant 10,121,868 - Qi , et al. November 6, 2	2018-11-06
Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method Grant 10,068,902 - Shen , et al. September 4, 2	2018-09-04
Multiple Fin heights with dielectric isolation Grant 10,068,810 - Wu , et al. September 4, 2	2018-09-04
Vertical-transport field-effect transistors with an etched-through source/drain cavity Grant 10,050,125 - Qi , et al. August 14, 2	2018-08-14
Method Of Forming Semiconductor Structure And Resulting Structure App 20180190792 - Peng; Jianwei ; et al.	2018-07-05
Multiple-layer Spacers For Field-effect Transistors App 20180151690 - Han; Tao ; et al.	2018-05-31
Multiple-layer spacers for field-effect transistors Grant 9,947,769 - Han , et al. April 17, 2	2018-04-17
Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device Grant 9,887,094 - Qi , et al. February 6, 2	2018-02-06
Semiconductor device and method of manufacturing the same Grant 9,847,225 - Cheng , et al. December 19, 2	2017-12-19
Multi-layer spacer used in finFET Grant 9,419,101 - Peng , et al. August 16, 2	2016-08-16
Gate structure having lightly doped region Grant 8,952,459 - Hing , et al. February 10, 2	2015-02-10
Gate Structure Having Lightly Doped Region App 20130334617 - HING; Fung Ka ; et al.	2013-12-19
Method for fabricating a gate structure Grant 8,535,998 - Hing , et al. September 17, 2	2013-09-17
Self-aligned two-step STI formation through dummy poly removal Grant 8,502,316 - Fung , et al. August 6, 2	2013-08-06
Semiconductor Device And Method Of Manufacturing The Same App 20130119444 - CHENG; Chun-Fai ; et al.	2013-05-16
Strained semiconductor device with recessed channel Grant 8,368,147 - Cheng , et al. February 5, 2	2013-02-05
Strained Semiconductor Device with Recessed Channel App 20110254105 - Cheng; Chun-Fai ; et al.	2011-10-20
Method For Fabricating A Gate Structure App 20110223752 - HING; Fung Ka ; et al.	2011-09-15
Self-Aligned Two-Step STI Formation Through Dummy Poly Removal App 20110193167 - Fung; Ka-Hing ; et al.	2011-08-11

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