Livingstone; William J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Livingstone; William J..The latest application filed is for "identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design".

Company Profile

0.6.5

Livingstone; William J. - Underhill VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design Grant 9,104,832 - Barwin, III , et al. August 11, 2	2015-08-11
Identifying And Mitigating Electromigration Failures In Signal Nets Of An Integrated Circuit Chip Design App 20150205906 - Barwin, III; John E. ; et al.	2015-07-23
Method to quickly estimate inductance for timing models Grant 7,750,648 - Foreman , et al. July 6, 2	2010-07-06
Methods for design rule checking with abstracted via obstructions Grant 7,725,850 - Darden , et al. May 25, 2	2010-05-25
Forming statistical model of independently variable parameters for timing analysis Grant 7,684,969 - Habitz , et al. March 23, 2	2010-03-23
Method To Quickly Estimate Inductance For Timing Models App 20090243630 - Foreman; Eric A. ; et al.	2009-10-01
Methods For Design Rule Checking With Abstracted Via Obstructions App 20090037857 - Darden; Laura R. ; et al.	2009-02-05
Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure Grant 7,464,359 - Habitz , et al. December 9, 2	2008-12-09
Method Of Reducing Correclated Coupling Between Nets App 20070226673 - Habitz; Peter A. ; et al.	2007-09-27
Forming statistical model of independently variable parameters for timing analysis App 20070055487 - Habitz; Peter A. ; et al.	2007-03-08
Method of automated design and checking for ESD robustness Grant 6,725,439 - Homsinger , et al. April 20, 2	2004-04-20

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