Liu; Yauh-Ching

Patent Applications and Registrations

Patent applications and USPTO patent grants for Liu; Yauh-Ching.The latest application filed is for "approach to avoid buckling in bpsg by using an intermediate barrier layer".

Company Profile

0.46.7

Liu; Yauh-Ching - Boise ID
Liu; Yauh-Ching - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Approach to avoid buckling in BPSG by using an intermediate barrier layer Grant 7,485,961 - Doan , et al. February 3, 2	2009-02-03
EEPROM transistor for a DRAM Grant 6,924,522 - Ma , et al. August 2, 2	2005-08-02
Fuse construction for integrated circuit structure having low dielectric constant dielectric material Grant 6,806,551 - Liu , et al. October 19, 2	2004-10-19
Approach to avoid buckling in BPSG by using an intermediate barrier layer App 20040188840 - Doan, Trung T. ; et al.	2004-09-30
Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls Grant 6,794,698 - Perng , et al. September 21, 2	2004-09-21
Laser-breakable fuse link with alignment and break point promotion structures Grant 6,770,947 - Giust , et al. August 3, 2	2004-08-03
Approach to avoid buckling BPSG by using an intermediate barrier layer Grant 6,690,044 - Doan , et al. February 10, 2	2004-02-10
Integrated capacitor and fuse Grant 6,627,968 - Cheng , et al. September 30, 2	2003-09-30
Fuse construction for integrated circuit structure having low dielectric constant dielectric material App 20030164532 - Liu, Yauh-Ching ; et al.	2003-09-04
Laser-breakable fuse link with alignment and break point promotion structures App 20030155629 - Giust, Gary K. ; et al.	2003-08-21
Integrated capacitor and fuse App 20030060009 - Cheng, Chuan-Cheng ; et al.	2003-03-27
Reduced soft error rate (SER) construction for integrated circuit structures Grant 6,472,715 - Liu , et al. October 29, 2	2002-10-29
Method of making EEPROM transistor for a DRAM App 20020135005 - Ma, Manny K. F. ; et al.	2002-09-26
Self-aligned fuse structure and method with dual-thickness dielectric Grant 6,413,848 - Giust , et al. July 2, 2	2002-07-02
Method of making EEPROM transistor for a DRAM Grant 6,391,755 - Ma , et al. May 21, 2	2002-05-21
DRAM cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation Grant 6,365,452 - Perng , et al. April 2, 2	2002-04-02
Method Of Making Eeprom Transistor For A Dram App 20020009831 - MA, MANNY K.F. ; et al.	2002-01-24
Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures App 20010000493 - Liu, Yauh-Ching ; et al.	2001-04-26
Silicide encapsulation of polysilicon gate and interconnect Grant 6,218,276 - Liu , et al. April 17, 2	2001-04-17
DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation Grant 6,177,699 - Perng , et al. January 23, 2	2001-01-23
Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures Grant 6,175,129 - Liu , et al. January 16, 2	2001-01-16
Integrated circuit having embedded memory with electromagnetic shield Grant 6,166,403 - Castagnetti , et al. December 26, 2	2000-12-26
Method of single step damascene process for deposition and global planarization Grant 6,090,239 - Liu , et al. July 18, 2	2000-07-18
Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls Grant 6,090,661 - Perng , et al. July 18, 2	2000-07-18
Metal-encapsulated polysilicon gate and interconnect Grant 6,037,233 - Liu , et al. March 14, 2	2000-03-14
Method of single step damascene process for deposition and global planarization Grant 6,004,880 - Liu , et al. December 21, 1	1999-12-21
EEPROM transistor for a DRAM Grant 5,973,344 - Ma , et al. October 26, 1	1999-10-26
Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step Grant 5,953,614 - Liu , et al. September 14, 1	1999-09-14
Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures Grant 5,905,280 - Liu , et al. May 18, 1	1999-05-18
Method of making EEPROM transistor for a DRAM Grant 5,723,375 - Ma , et al. March 3, 1	1998-03-03
Method of forming a field effect transistor Grant 5,688,700 - Kao , et al. November 18, 1	1997-11-18
Approach to avoid buckling in BPSG by using an intermediate barrier layer Grant 5,372,974 - Doan , et al. December 13, 1	1994-12-13
Stacked V-cell capacitor using a disposable outer digit line spacer Grant 5,321,648 - Dennison , et al. June 14, 1	1994-06-14
Stacked delta cell capacitor Grant 5,321,649 - Lee , et al. June 14, 1	1994-06-14
DRAM stacked capacitor fabrication process Grant 5,262,343 - Rhodes , et al. November 16, 1	1993-11-16
Lateral extension stacked capacitor Grant 5,236,860 - Fazan , et al. August 17, 1	1993-08-17
Stacked comb spacer capacitor Grant 5,234,855 - Rhodes , et al. * August 10, 1	1993-08-10
Stacked V-cell capacitor Grant 5,219,778 - Dennison , et al. June 15, 1	1993-06-15
Method of making a stacked capacitor dram cell Grant 5,196,364 - Fazan , et al. March 23, 1	1993-03-23
Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor Grant 5,170,233 - Liu , et al. December 8, 1	1992-12-08
Double DRAM cell Grant 5,122,476 - Fazan , et al. June 16, 1	1992-06-16
Mushroom double stacked capacitor Grant 5,108,943 - Sandhu , et al. * April 28, 1	1992-04-28
Method of making stacked surrounding reintrant wall capacitor Grant 5,100,825 - Fazan , et al. March 31, 1	1992-03-31
Method for forming low resistance DRAM digit-line Grant 5,084,406 - Rhodes , et al. January 28, 1	1992-01-28
Process to fabricate a double ring stacked cell structure Grant 5,084,405 - Fazan , et al. January 28, 1	1992-01-28
Method of making stacked textured container capacitor Grant 5,082,797 - Chan , et al. January 21, 1	1992-01-21
Enclosed ferroelectric stacked capacitor Grant 5,081,559 - Fazan , et al. January 14, 1	1992-01-14
Method for formation of a stacked capacitor Grant 5,061,650 - Dennison , et al. October 29, 1	1991-10-29
Double DRAM cell Grant 5,057,888 - Fazan , et al. October 15, 1	1991-10-15
Method of making stacked E-cell capacitor DRAM cell Grant 5,053,351 - Fazan , et al. October 1, 1	1991-10-01
Method for formation of a stacked capacitor Grant 5,049,517 - Liu , et al. September 17, 1	1991-09-17
Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography Grant 5,013,680 - Lowrey , et al. May 7, 1	1991-05-07
Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers Grant 4,981,810 - Fazan , et al. January 1, 1	1991-01-01

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