Liu; Peichun Peter

Patent Applications and Registrations

Patent applications and USPTO patent grants for Liu; Peichun Peter.The latest application filed is for "controlling bandwidth reservations method and apparatus".

Company Profile

0.30.22

Liu; Peichun Peter - Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Controlling bandwidth reservations method and apparatus Grant 8,611,368 - Asano , et al. December 17, 2	2013-12-17
Controlling bandwidth reservations method and apparatus Grant 8,483,227 - Asano , et al. July 9, 2	2013-07-09
Controlling Bandwidth Reservations Method And Apparatus App 20110246695 - Asano; Shigehiro ; et al.	2011-10-06
Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment Grant 7,725,618 - Day , et al. May 25, 2	2010-05-25
Methods and apparatus for list transfers using DMA transfers in a multi-processor system Grant 7,698,473 - Yamazaki , et al. April 13, 2	2010-04-13
Method to provide cache management commands for a DMA controller Grant 7,657,667 - Johns , et al. February 2, 2	2010-02-02
System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus App 20090077322 - Johns; Charles Ray ; et al.	2009-03-19
Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes Grant 7,287,103 - Ganfield , et al. October 23, 2	2007-10-23
Establishing command order in an out of order DMA command queue Grant 7,243,200 - Day , et al. July 10, 2	2007-07-10
Round robin selection logic improves area efficiency and circuit speed Grant 7,231,479 - Handlogten , et al. June 12, 2	2007-06-12
Proxy direct memory access Grant 7,225,277 - Johns , et al. May 29, 2	2007-05-29
Array read access control using MUX select signal gating of the read port Grant 7,187,614 - Cottier , et al. March 6, 2	2007-03-06
Method to handle rambus write mask App 20060265546 - Ganfield; Paul Allen ; et al.	2006-11-23
Systems and methods for bandwidth shaping Grant 7,107,376 - Asano , et al. September 12, 2	2006-09-12
Methods and apparatus for list transfers using DMA transfers in a multi-processor system App 20060149861 - Yamazaki; Takeshi ; et al.	2006-07-06
Implementation of a pseudo-LRU algorithm in a partitioned cache Grant 7,069,390 - Chen , et al. June 27, 2	2006-06-27
Pseudo-LRU for a locking cache Grant 7,055,004 - DeMent , et al. May 30, 2	2006-05-30
Ring-topology based multiprocessor data access bus Grant 7,043,579 - Dhong , et al. May 9, 2	2006-05-09
Array read access control using MUX select signal gating of the read port App 20060083074 - Cottier; Scott Raymond ; et al.	2006-04-20
Read/write methods for limited memory access applications App 20060023552 - Aipperspach; Anthony Gus ; et al.	2006-02-02
DMAC issue mechanism via streaming ID method App 20060026308 - King; Matthew Edward ; et al.	2006-02-02
Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment App 20060026309 - Day; Michael Norman ; et al.	2006-02-02
Implementation and management of moveable buffers in cache system App 20060015689 - Okawa; Yasukichi ; et al.	2006-01-19
Establishing command order in an out of order DMA command queue App 20060015652 - Day; Michael Norman ; et al.	2006-01-19
Microprocessor chip simultaneous switching current reduction method and apparatus Grant 6,983,387 - Boerstler , et al. January 3, 2	2006-01-03
System and method for identifying and accessing streaming data in a locked portion of a cache Grant 6,961,820 - Day , et al. November 1, 2	2005-11-01
Method to provide cache management commands for a DMA controller App 20050216610 - Johns, Charles Ray ; et al.	2005-09-29
Implementation of an LRU and MRU algorithm in a partitioned cache Grant 6,931,493 - Johns , et al. August 16, 2	2005-08-16
Systems and methods for bandwidth shaping App 20050165987 - Asano, Shigehiro ; et al.	2005-07-28
Round robin selection logic improves area efficiency and circuit speed App 20050138055 - Handlogten, Glen Howard ; et al.	2005-06-23
Controlling bandwidth reservations method and apparatus App 20050111354 - Asano, Shigehiro ; et al.	2005-05-26
Proxy direct memory access App 20050055478 - Johns, Charles Ray ; et al.	2005-03-10
Pseudo-LRU for a locking cache App 20050055506 - DeMent, Jonathan James ; et al.	2005-03-10
Implementation of a pseudo-LRU algorithm in a partitioned cache App 20050055513 - Chen, Wen-Tzer Thomas ; et al.	2005-03-10
On-chip data transfer in multi-processor system Grant 6,820,143 - Day , et al. November 16, 2	2004-11-16
Streaming data using locking cache App 20040162946 - Day, Michael Norman ; et al.	2004-08-19
Implementation of an LRU and MRU algorithm in a partitioned cache App 20040143706 - Johns, Charles Ray ; et al.	2004-07-22
On-chip data transfer in multi-processor system App 20040117520 - Day, Michael Norman ; et al.	2004-06-17
Ring-topology based multiprocessor data access bus App 20040111546 - Dhong, Sang Hoo ; et al.	2004-06-10
Microprocessor chip simultaneous switching current reduction method and apparatus App 20040078613 - Boerstler, David William ; et al.	2004-04-22
Method and system for pre-fetch cache interrogation using snoop port Grant 6,202,128 - Chan , et al. March 13, 2	2001-03-13
Token mechanism for cache-line replacement within a cache memory having redundant cache lines Grant 6,041,390 - Liu , et al. March 21, 2	2000-03-21
Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator Grant 5,937,429 - Kumar , et al. August 10, 1	1999-08-10
Cache sub-array arbitration Grant 5,905,999 - Liu , et al. May 18, 1	1999-05-18
Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit Grant 5,890,221 - Liu , et al. March 30, 1	1999-03-30
Mechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memory Grant 5,802,567 - Liu , et al. September 1, 1	1998-09-01
Single-cycle multi-accessible interleaved cache Grant 5,761,714 - Liu , et al. June 2, 1	1998-06-02
High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses Grant 5,752,260 - Liu May 12, 1	1998-05-12
Method and system for efficient miss sequence cache line allocation utilizing an allocation control cell state to enable a selected match line Grant 5,668,972 - Liu , et al. September 16, 1	1997-09-16
Method and system for concurrent access in a data cache array utilizing multiple match line selection paths Grant 5,640,534 - Liu , et al. June 17, 1	1997-06-17

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