Liu; Michael S
Patent Applications and Registrations
Patent applications and USPTO patent grants for Liu; Michael S.The latest application filed is for "non-planar silicon-on-insulator device that includes an "area-efficient" body tie".
- Liu; Michael S - Bloomington MN
- Liu; Michael S. - Bloomington MN
- Liu; Michael S. - Hennepin County MN
| Patent | Date |
|---|---|
| Method of fabricating total dose hard and thermal neutron hard integrated circuits Grant 8,759,903 - Liu , et al. June 24, 2 | 2014-06-24 |
| Non-planar silicon-on-insulator device that includes an "area-efficient" body tie Grant 7,679,139 - Larsen , et al. March 16, 2 | 2010-03-16 |
| Method and apparatus for regulating photo currents induced by dose rate events Grant 7,589,308 - Liu , et al. September 15, 2 | 2009-09-15 |
| Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie App 20090065866 - Larsen; Bradley J. ; et al. | 2009-03-12 |
| Method and Apparatus for Regulating Photo Currents App 20080054360 - Liu; Harry HL ; et al. | 2008-03-06 |
| Simulating a dose rate event in a circuit design Grant 7,322,015 - Liu , et al. January 22, 2 | 2008-01-22 |
| System and method for hardening MRAM bits Grant 7,286,393 - Hynes , et al. October 23, 2 | 2007-10-23 |
| Radiation-hardened memory element with multiple delay elements App 20070242537 - Golke; Keith W. ; et al. | 2007-10-18 |
| System and method for hardening MRAM bits App 20060221675 - Hynes; Owen J. ; et al. | 2006-10-05 |
| Dose rate simulation App 20060145086 - Liu; Harry H.L. ; et al. | 2006-07-06 |
| SEU resistant SRAM using feedback MOSFET Grant 6,775,178 - Liu , et al. August 10, 2 | 2004-08-10 |
| High speed SOI transistors App 20030189227 - Liu, Michael S. ; et al. | 2003-10-09 |
| SEU resistant SRAM using feedback MOSFET App 20030189847 - Liu, Michael S. ; et al. | 2003-10-09 |
| SOI substrate fabrication Grant 5,659,192 - Sarma , et al. August 19, 1 | 1997-08-19 |
| High resolution active matrix LCD cell design Grant 5,536,950 - Liu , et al. July 16, 1 | 1996-07-16 |
| Method for electrically characterizing the insulator in SOI devices Grant 5,519,336 - Liu , et al. May 21, 1 | 1996-05-21 |
| SOI substrate fabrication Grant 5,344,524 - Sharma , et al. September 6, 1 | 1994-09-06 |
| Integrated infrared sensitive bolometers Grant 5,260,225 - Liu , et al. November 9, 1 | 1993-11-09 |
| Fabrication of stabilized polysilicon resistors for SEU control Grant 5,212,108 - Liu , et al. May 18, 1 | 1993-05-18 |
| Method for forming variable width isolation structures Grant 5,017,999 - Roisen , et al. May 21, 1 | 1991-05-21 |
| Method of making planarized, self-aligned bipolar integrated circuits Grant 5,008,208 - Liu , et al. April 16, 1 | 1991-04-16 |
| Three-dimensional CMOS using selective epitaxial growth Grant 4,686,758 - Liu , et al. August 18, 1 | 1987-08-18 |
| Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs Grant 4,551,394 - Betsch , et al. November 5, 1 | 1985-11-05 |
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