| Patent | Date |
|---|
Light emitting diode driving circuit with low harmonic distortion
Grant 10,694,595 - Lin , et al. | 2020-06-23 |
Light emitting diode driving circuit for reducing flicker effect
Grant 10,321,526 - Lin , et al. | 2019-06-11 |
Transistor structures and fabrication methods thereof
Grant 10,204,991 - Wu , et al. Feb | 2019-02-12 |
Light Emitting Diode Driving Circuit With Low Harmonic Distortion
App 20180324909 - Lin; Yu-Chen ; et al. | 2018-11-08 |
Light Emitting Diode Driving Circuit
App 20180103517 - Lin; Yu-Chen ; et al. | 2018-04-12 |
Light Emitting Diode Driving Circuit For Reducing Flicker Effect
App 20180103514 - Lin; Yu-Chen ; et al. | 2018-04-12 |
Light emitting diode driving circuit
Grant 9,942,957 - Lin , et al. April 10, 2 | 2018-04-10 |
Transistor Structures And Fabrication Methods Thereof
App 20170213890 - WU; Xusheng ; et al. | 2017-07-27 |
Conformal nitridation of one or more fin-type transistor layers
Grant 9,698,269 - Tong , et al. July 4, 2 | 2017-07-04 |
Devices comprising high-K dielectric layer and methods of forming same
Grant 9,673,039 - Ray , et al. June 6, 2 | 2017-06-06 |
Transistor structures and fabrication methods thereof
Grant 9,647,073 - Wu , et al. May 9, 2 | 2017-05-09 |
Methods for fabricating integrated circuits using self-aligned quadruple patterning
Grant 9,620,380 - Dai , et al. April 11, 2 | 2017-04-11 |
Reducing liner corrosion during metallization of semiconductor devices
Grant 9,595,493 - Sun , et al. March 14, 2 | 2017-03-14 |
Reducing Liner Corrosion During Metallization Of Semiconductor Devices
App 20170047282 - SUN; Zhiguo ; et al. | 2017-02-16 |
Different Height Of Fins In Semiconductor Structure
App 20160315084 - WU; Xusheng ; et al. | 2016-10-27 |
Methods of fabricating integrated circuits
Grant 9,472,465 - Lee , et al. October 18, 2 | 2016-10-18 |
Liner and cap layer for placeholder source/drain contact structure planarization and replacement
Grant 9,466,723 - Huang , et al. October 11, 2 | 2016-10-11 |
Devices Comprising High-k Dielectric Layer And Methods Of Forming Same
App 20160284540 - RAY; Shishir ; et al. | 2016-09-29 |
Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits
Grant 9,455,201 - Joshi , et al. September 27, 2 | 2016-09-27 |
Method for forming air gap structure using carbon-containing spacer
Grant 9,443,956 - Yu , et al. September 13, 2 | 2016-09-13 |
Integrated circuits and methods for fabricating integrated circuits with active area protection
Grant 9,419,126 - Yang , et al. August 16, 2 | 2016-08-16 |
Fabricating Fin Structures With Doped Middle Portions
App 20160225771 - WU; Xusheng ; et al. | 2016-08-04 |
Method for forming single diffusion breaks between finFET devices and the resulting devices
Grant 9,406,676 - Yu , et al. August 2, 2 | 2016-08-02 |
Method for reducing gate height variation due to overlapping masks
Grant 9,401,416 - Yu , et al. July 26, 2 | 2016-07-26 |
Method For Forming Single Diffusion Breaks Between Finfet Devices And The Resulting Devices
App 20160190130 - Yu; Hong ; et al. | 2016-06-30 |
Conformal Nitridation Of One Or More Fin-type Transistor Layers
App 20160190324 - TONG; Wei Hua ; et al. | 2016-06-30 |
T-shaped fin isolation region and methods of fabrication
Grant 9,373,535 - Shen , et al. June 21, 2 | 2016-06-21 |
Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch
Grant 9,368,342 - Huang , et al. June 14, 2 | 2016-06-14 |
Method For Forming Air Gap Structure Using Carbon-containing Spacer
App 20160163816 - Yu; Hong ; et al. | 2016-06-09 |
Method For Reducing Gate Height Variation Due To Overlapping Masks
App 20160163830 - Yu; Hong ; et al. | 2016-06-09 |
Integrated circuit having multiple threshold voltages
Grant 9,362,180 - Lee , et al. June 7, 2 | 2016-06-07 |
Fabricating fin structures with doped middle portions
Grant 9,343,371 - Wu , et al. May 17, 2 | 2016-05-17 |
Transistor Structures And Fabrication Methods Thereof
App 20160126316 - WU; Xusheng ; et al. | 2016-05-05 |
T-shaped Fin Isolation Region And Methods Of Fabrication
App 20160111320 - SHEN; Hongliang ; et al. | 2016-04-21 |
Conformal nitridation of one or more fin-type transistor layers
Grant 9,312,145 - Tong , et al. April 12, 2 | 2016-04-12 |
Facilitating Fabricating Gate-all-around Nanowire Field-effect Transistors
App 20160099344 - LIU; Jin Ping ; et al. | 2016-04-07 |
Facilitating fabricating gate-all-around nanowire field-effect transistors
Grant 9,263,520 - Liu , et al. February 16, 2 | 2016-02-16 |
Semiconductor device and methods of forming fins and gates with ultraviolet curing
Grant 9,236,481 - Zang , et al. January 12, 2 | 2016-01-12 |
Uniform gate height for mixed-type non-planar semiconductor devices
Grant 9,230,822 - Yu , et al. January 5, 2 | 2016-01-05 |
Uniform Gate Height For Mixed-type Non-planar Semiconductor Devices
App 20150364336 - YU; Hong ; et al. | 2015-12-17 |
Methods Of Fabricating Defect-free Semiconductor Structures
App 20150357292 - LIU; Hung-Wei ; et al. | 2015-12-10 |
Devices And Methods Of Forming Bulk Finfets With Lateral Seg For Source And Drain On Dielectrics
App 20150357332 - LIU; Jin Ping ; et al. | 2015-12-10 |
Integrated circuits with relaxed silicon / germanium fins
Grant 9,196,710 - Wei , et al. November 24, 2 | 2015-11-24 |
Devices And Methods Of Forming Finfets With Self Aligned Fin Formation
App 20150333067 - WAN; Jing ; et al. | 2015-11-19 |
Methods Of Fabricating Integrated Circuits
App 20150325681 - Lee; Bongki ; et al. | 2015-11-12 |
Defect-free Relaxed Covering Layer On Semiconductor Substrate With Lattice Mismatch
App 20150295047 - HUANG; Haigou ; et al. | 2015-10-15 |
Integrated Circuits With Stressed Semiconductor Substrates And Processes For Preparing Integrated Circuits Including The Stressed Semiconductor Substrates
App 20150287824 - Ray; Shishir ; et al. | 2015-10-08 |
Devices and methods of forming finFETs with self aligned fin formation
Grant 9,147,696 - Wan , et al. September 29, 2 | 2015-09-29 |
Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
Grant 9,142,673 - Liu , et al. September 22, 2 | 2015-09-22 |
Methods of fabricating defect-free semiconductor structures
Grant 9,142,422 - Liu , et al. September 22, 2 | 2015-09-22 |
Containment structure for epitaxial growth in non-planar semiconductor structure
Grant 9,142,640 - Wu , et al. September 22, 2 | 2015-09-22 |
Conformal Nitridation Of One Or More Fin-type Transistor Layers
App 20150255277 - TONG; Wei Hua ; et al. | 2015-09-10 |
Replacement low-K spacer
Grant 9,129,987 - Wan , et al. September 8, 2 | 2015-09-08 |
Integrated Circuit Having Multiple Threshold Voltages
App 20150243563 - LEE; Bongki ; et al. | 2015-08-27 |
Integration Method For Fabrication Of Metal Gate Based Multiple Threshold Voltage Devices And Circuits
App 20150243652 - JOSHI; Manoj ; et al. | 2015-08-27 |
Integrated Circuits With Relaxed Silicon / Germanium Fins
App 20150228755 - Wei; Andy ; et al. | 2015-08-13 |
Replacement Low-k Spacer
App 20150214330 - WAN; Jing ; et al. | 2015-07-30 |
Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same
Grant 9,087,870 - Tong , et al. July 21, 2 | 2015-07-21 |
Strained Fin Structures And Methods Of Fabrication
App 20150194307 - GAIRE; Churamani ; et al. | 2015-07-09 |
Method of fabricating an interlayer structure of increased elasticity modulus
Grant 9,076,645 - Ray , et al. July 7, 2 | 2015-07-07 |
Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
Grant 9,040,380 - Hu , et al. May 26, 2 | 2015-05-26 |
Methods Of Fabricating Defect-free Semiconductor Structures
App 20150123250 - LIU; Hung-Wei ; et al. | 2015-05-07 |
Facilitating Fabricating Gate-all-around Nanowire Field-effect Transistors
App 20150104918 - LIU; Jin Ping ; et al. | 2015-04-16 |
Devices And Methods Of Forming Finfets With Self Aligned Fin Formation
App 20150091094 - WAN; Jing ; et al. | 2015-04-02 |
Integrated Circuits Having Laterally Confined Epitaxial Material Overlying Fin Structures And Methods For Fabricating Same
App 20150069515 - Hu; Xiang ; et al. | 2015-03-12 |
Devices And Methods Of Forming Bulk Finfets With Lateral Seg For Source And Drain On Dielectrics
App 20150035018 - LIU; Jin Ping ; et al. | 2015-02-05 |
Method Of Forming Fins With Recess Shapes
App 20150017774 - TONG; Wei Hua ; et al. | 2015-01-15 |
Integrated Circuits Including Finfet Devices With Shallow Trench Isolation That Includes A Thermal Oxide Layer And Methods For Making The Same
App 20140353795 - Tong; Wei Hua ; et al. | 2014-12-04 |
Integrated Circuits And Methods For Fabricating Integrated Circuits With Active Area Protection
App 20140264613 - Yang; Xiaodong ; et al. | 2014-09-18 |
Implant damage control by in-situ C doping during sige epitaxy for device applications
Grant 8,790,980 - Liu , et al. July 29, 2 | 2014-07-29 |
Strained channel transistor structure and method
Grant 8,754,447 - Liu , et al. June 17, 2 | 2014-06-17 |
Implant Damage Control By In-situ C Doping During Sige Epitaxy For Device Applications
App 20140159113 - LIU; Jin Ping ; et al. | 2014-06-12 |
Implant damage control by in-situ C doping during sige epitaxy for device applications
Grant 8,652,892 - Liu , et al. February 18, 2 | 2014-02-18 |
Integrated circuit system with carbon and non-carbon silicon
Grant 8,105,955 - Liu , et al. January 31, 2 | 2012-01-31 |
Implant Damage Control By In-situ C Doping During Sige Epitaxy For Device Applications
App 20110223737 - LIU; Jin Ping ; et al. | 2011-09-15 |
Implant damage control by in-situ C doping during SiGe epitaxy for device applications
Grant 7,947,546 - Liu , et al. May 24, 2 | 2011-05-24 |
Integration for buried epitaxial stressor
Grant 7,863,141 - Liu January 4, 2 | 2011-01-04 |
Strained Channel Transistor Structure And Method
App 20100308374 - LIU; Jin Ping ; et al. | 2010-12-09 |
Strained channel transistor structure and method
Grant 7,776,699 - Liu , et al. August 17, 2 | 2010-08-17 |
Integrated Circuit System Employing Stress-engineered Layers
App 20100109045 - Liu; Jin Ping ; et al. | 2010-05-06 |
Strained Channel Transistor Structure And Method
App 20090194788 - LIU; Jin Ping ; et al. | 2009-08-06 |
Integrated Circuit System Employing Diffused Source/drain Extensions
App 20090146181 - Lai; Chung Woh ; et al. | 2009-06-11 |
Integrated Circuit System With Carbon And Non-carbon Silicon
App 20080121926 - Liu; Jin Ping ; et al. | 2008-05-29 |
Integration for buried epitaxial stressor
App 20080026540 - Liu; Jin Ping | 2008-01-31 |
Implant damage control by in-situ C doping during SiGe epitaxy for device applications
App 20070096149 - Liu; Jin Ping ; et al. | 2007-05-03 |
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
Grant 7,166,522 - Liu , et al. January 23, 2 | 2007-01-23 |
Silicon-germanium virtual substrate and method of fabricating the same
Grant 7,064,037 - Liu June 20, 2 | 2006-06-20 |
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
Grant 6,995,078 - Liu , et al. February 7, 2 | 2006-02-07 |
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
App 20050164473 - Liu, Jin Ping ; et al. | 2005-07-28 |
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
App 20050164436 - Liu, Jin Ping ; et al. | 2005-07-28 |
Silicon - germanium virtual substrate and method of fabricating the same
App 20050153495 - Liu, Jin Ping | 2005-07-14 |
| 