loadpatents
name:-0.010104894638062
name:-0.0077359676361084
name:-0.00059604644775391
Liu; Heng-Kai Patent Filings

Liu; Heng-Kai

Patent Applications and Registrations

Patent applications and USPTO patent grants for Liu; Heng-Kai.The latest application filed is for "method, system and computer readable medium using stitching for mask assignment of patterns".

Company Profile
0.12.10
  • Liu; Heng-Kai - Pingzhen TW
  • LIU; Heng-Kai - Pingzhen City TW
  • Liu; Heng-Kai - Yangmei Township N/A TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method, system and computer readable medium using stitching for mask assignment of patterns
Grant 9,824,968 - Yu-Tseng , et al. November 21, 2
2017-11-21
Wiring layout having differently shaped vias
Grant 9,685,395 - Chuang , et al. June 20, 2
2017-06-20
Partitioning method and system for 3D IC
Grant 9,514,261 - Liu , et al. December 6, 2
2016-12-06
Method, System And Computer Readable Medium Using Stitching For Mask Assignment Of Patterns
App 20160240474 - YU-TSENG; Hsien ;   et al.
2016-08-18
Method, system and computer readable medium using stitching for mask assignment of patterns
Grant 9,342,646 - Yu-Tseng , et al. May 17, 2
2016-05-17
Wiring Layout Having Differently Shaped Vias
App 20150179550 - Chuang; Harry-Hak-Lay ;   et al.
2015-06-25
Partitioning Method And System For 3d Ic
App 20150149977 - LIU; Heng Kai ;   et al.
2015-05-28
Wiring layout having differently shaped vias
Grant 8,981,562 - Chuang , et al. March 17, 2
2015-03-17
Partitioning method and system for 3D IC
Grant 8,966,426 - Liu , et al. February 24, 2
2015-02-24
Eda Tool And Method, And Integrated Circuit Formed By The Method
App 20140229902 - YU-TSENG; Hsien ;   et al.
2014-08-14
Method and system for layout parasitic estimation
Grant 8,806,414 - Huang , et al. August 12, 2
2014-08-12
EDA tool and method, and integrated circuit formed by the method
Grant 8,745,552 - Tseng , et al. June 3, 2
2014-06-03
Eda Tool And Method, And Integrated Circuit Formed By The Method
App 20130320555 - YU-TSENG; Hsien ;   et al.
2013-12-05
Method And System For Layout Parasitic Estimation
App 20130326447 - HUANG; Mu-Jen ;   et al.
2013-12-05
Method for Improving Design Window
App 20080237885 - Chuang; Harry ;   et al.
2008-10-02
Method for improving design window
Grant 7,404,167 - Chuang , et al. July 22, 2
2008-07-22
Method for improving design window
App 20060188824 - Chuang; Harry ;   et al.
2006-08-24

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