LIOU; Shiann-Ming

Patent Applications and Registrations

Patent applications and USPTO patent grants for LIOU; Shiann-Ming.The latest application filed is for "packaging-level chip and chip module packaged with magnetic cover, and electronic product".

Company Profile

1.89.43

LIOU; Shiann-Ming - Shanghai CN
Liou; Shiann-Ming - Campbell CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Packaging-level Chip And Chip Module Packaged With Magnetic Cover, And Electronic Product App 20220270951 - BAI; Yanwen ; et al.	2022-08-25
Multilayer Circuit Board App 20220217851 - BAI; Yanwen ; et al.	2022-07-07
Removable non-volatile storage card Grant 11,308,380 - Mathew , et al. April 19, 2	2022-04-19
Ground reference shape for high speed interconnect Grant 11,276,655 - Liou , et al. March 15, 2	2022-03-15
Circuit Assembly With Thermal Coating In Contact With Exposed Metal Edges App 20220068749 - BAI; Yanwen ; et al.	2022-03-03
Embedded Microstrip With Open Slot For High Speed Signal Traces App 20210392742 - LIOU; Shiann-Ming ; et al.	2021-12-16
Ground Reference Shape For High Speed Interconnect App 20210366848 - LIOU; Shiann-Ming ; et al.	2021-11-25
Semiconductor die with hybrid wire bond pads Grant 11,043,435 - Chen , et al. June 22, 2	2021-06-22
Leadframe with improved half-etch layout to reduce defects caused during singulation Grant 10,128,171 - Kao , et al. November 13, 2	2018-11-13
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate Grant 9,768,144 - Wu , et al. September 19, 2	2017-09-19
Dual row quad flat no-lead semiconductor package Grant 9,666,510 - Liu , et al. May 30, 2	2017-05-30
Package-on-package structures Grant 9,666,571 - Kao , et al. May 30, 2	2017-05-30
Packaging Arrangements Including A Serializing Dram Interface Die App 20170047305 - Liu; Chenglin ; et al.	2017-02-16
Pad configurations for an electronic package assembly Grant 9,543,236 - Sutardja , et al. January 10, 2	2017-01-10
Dual Row Quad Flat No-lead Semiconductor Package App 20160358845 - Liu; Chenglin ; et al.	2016-12-08
Method For Forming A Via Structure Using A Double-side Laser Process App 20160353585 - Kao; Huahung ; et al.	2016-12-01
Dual row quad flat no-lead semiconductor package Grant 9,425,139 - Liu , et al. August 23, 2	2016-08-23
Pad Configurations For An Electronic Package Assembly App 20160240459 - Sutardja; Sehat ; et al.	2016-08-18
Recessed semiconductor substrates and associated techniques Grant 9,391,045 - Wu , et al. July 12, 2	2016-07-12
Ball Grid Array Package Substrate With Through Holes And Method Of Forming Same App 20160196986 - Liou; Shiann-Ming ; et al.	2016-07-07
Package Assembly Including A Semiconductor Substrate In Which A First Portion Of A Surface Of The Semiconductor Substrate Is Recessed Relative To A Second Portion Of The Surface Of The Semiconductor Substrate To Form A Recessed Region In The Semiconductor Substrate App 20160155732 - Wu; Albert ; et al.	2016-06-02
Interconnect layouts for electronic assemblies Grant 9,355,951 - Kao , et al. May 31, 2	2016-05-31
Pad configurations for an electronic package assembly Grant 9,331,052 - Sutardja , et al. May 3, 2	2016-05-03
Package-on-package Structures App 20160093602 - Kao; Huahung ; et al.	2016-03-31
Ball grid array package substrate with through holes and method of forming same Grant 9,288,909 - Liou , et al. March 15, 2	2016-03-15
Package assembly having a semiconductor substrate Grant 9,275,929 - Liou , et al. March 1, 2	2016-03-01
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate Grant 9,257,410 - Wu , et al. February 9, 2	2016-02-09
Method for forming semiconductor layout Grant 9,252,115 - Ngo , et al. February 2, 2	2016-02-02
Semiconductor die having lead wires formed over a circuit in a shielded area Grant 9,240,372 - Liou January 19, 2	2016-01-19
Semiconductor package Grant 9,224,677 - Liou , et al. December 29, 2	2015-12-29
Package-on-package structures Grant 9,209,163 - Kao , et al. December 8, 2	2015-12-08
Semiconductor Package With A Semiconductor Die Embedded Within Substrates App 20150311147 - Wu; Albert ; et al.	2015-10-29
Attaching passive components to a semiconductor package Grant 9,171,744 - Liou , et al. October 27, 2	2015-10-27
Recessed Semiconductor Substrates And Associated Techniques App 20150279806 - Wu; Albert ; et al.	2015-10-01
Method For Forming A Via Structure Using A Double-side Laser Process App 20150257281 - Kao; Huahung ; et al.	2015-09-10
Formation of package pins in semiconductor packaging Grant 9,123,699 - Liu , et al. September 1, 2	2015-09-01
Package Assembly Having A Semiconductor Substrate App 20150221577 - Liou; Shiann-Ming ; et al.	2015-08-06
Attaching Passive Components To A Semiconductor Package App 20150200114 - Liou; Shiann-Ming ; et al.	2015-07-16
Semiconductor package with a semiconductor die embedded within substrates Grant 9,070,679 - Wu , et al. June 30, 2	2015-06-30
Method for forming one or more vias through a semiconductor substrate and forming a redistribution layer on the semiconductor substrate Grant 9,064,860 - Liou , et al. June 23, 2	2015-06-23
Recessed semiconductor substrates and associated techniques Grant 9,034,730 - Wu , et al. May 19, 2	2015-05-19
Etched hybrid die package Grant 8,999,755 - Liu , et al. April 7, 2	2015-04-07
Attaching passive components to a semiconductor package Grant 8,987,830 - Liou , et al. March 24, 2	2015-03-24
Pad Configurations For An Electronic Package Assembly App 20150035160 - Sutardja; Sehat ; et al.	2015-02-05
Single layer BGA substrate process Grant 8,940,585 - Liou , et al. January 27, 2	2015-01-27
Leadless multi-chip module structure Grant 8,912,664 - Liou , et al. December 16, 2	2014-12-16
Thermal enhanced package Grant 8,900,932 - Liu , et al. December 2, 2	2014-12-02
Integrated circuit packaging configurations Grant 8,884,419 - Liou , et al. November 11, 2	2014-11-11
Pad configurations for an electronic package assembly Grant 8,860,193 - Sutardja , et al. October 14, 2	2014-10-14
Chip on leads Grant 8,809,118 - Liu , et al. August 19, 2	2014-08-19
Semiconductor layout Grant 8,796,868 - Ngo , et al. August 5, 2	2014-08-05
Single Layer Bga Substrate Process App 20140206152 - Liou; Shiann-Ming ; et al.	2014-07-24
Through via semiconductor die with backside redistribution layer Grant 8,754,506 - Liou , et al. June 17, 2	2014-06-17
Package-on-package Structures App 20140151880 - Kao; Huahung ; et al.	2014-06-05
Placing heat sink into packaging by strip formation assembly Grant 8,741,694 - Chen , et al. June 3, 2	2014-06-03
Techniques And Configurations For Recessed Semiconductor Substrates App 20140124961 - WU; Albert ; et al.	2014-05-08
Stack die structure for stress reduction and facilitation of electromagnetic shielding Grant 8,686,547 - Kao , et al. April 1, 2	2014-04-01
Single layer BGA substrate process Grant 8,673,689 - Liou , et al. March 18, 2	2014-03-18
Etched hybrid die package Grant 8,673,687 - Liu , et al. March 18, 2	2014-03-18
Dual Row Quad Flat No-lead Semiconductor Package App 20140069703 - Liu; Chenglin ; et al.	2014-03-13
Leadless multi-chip module structure Grant 8,669,139 - Liou , et al. March 11, 2	2014-03-11
Semiconductor device having lead wires connecting bonding pads formed on opposite sides of a core region forming a shield area Grant 8,637,975 - Liou January 28, 2	2014-01-28
Method of stacking flip-chip on wire-bonded chip Grant 8,624,377 - Liou , et al. January 7, 2	2014-01-07
Placing heat sink into packaging by strip formation assembly Grant 8,581,374 - Chen , et al. November 12, 2	2013-11-12
Semiconductor packaging with internal wiring bus Grant 8,518,742 - Liu , et al. August 27, 2	2013-08-27
Ball Grid Array Package Substrate With Through Holes And Method Of Forming Same App 20130193572 - Liou; Shiann-Ming ; et al.	2013-08-01
Semiconductor package Grant 8,482,112 - Liou , et al. July 9, 2	2013-07-09
Integrated circuit packaging configurations Grant 8,471,376 - Liou , et al. June 25, 2	2013-06-25
Method Of Stacking Flip-chip On Wire-bonded Chip App 20130147025 - Liou; Shiann-Ming ; et al.	2013-06-13
Package-on-package Structures App 20130043587 - Kao; Huahung ; et al.	2013-02-21
Chip On Leads App 20130045573 - Liu; Chenglin ; et al.	2013-02-21
Method of stacking flip-chip on wire-bonded chip Grant 8,372,692 - Liou , et al. February 12, 2	2013-02-12
Thermal enhanced package Grant 8,357,568 - Liu , et al. January 22, 2	2013-01-22
Leadless multi-chip module structure Grant 8,358,013 - Liou , et al. January 22, 2	2013-01-22
Thermal Enhanced Package App 20130011964 - Liu; Chenglin ; et al.	2013-01-10
Pre-formed conductive bumps on bonding pads Grant 8,319,353 - Liou , et al. November 27, 2	2012-11-27
Chip on leads Grant 8,294,248 - Liu , et al. October 23, 2	2012-10-23
Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads Grant 8,258,616 - Liou September 4, 2	2012-09-04
Single Layer Bga Substrate Process App 20120196407 - Liou; Shiann-Ming ; et al.	2012-08-02
Pad Configurations For An Electronic Package Assembly App 20110298117 - Sutardja; Sehat ; et al.	2011-12-08
Pre-formed conductive bumps on bonding pads Grant 8,030,098 - Liou , et al. October 4, 2	2011-10-04
Semiconductor package Grant 8,022,522 - Liou , et al. September 20, 2	2011-09-20
Pillar structure on bump pad Grant 7,999,395 - Kao , et al. August 16, 2	2011-08-16
Recessed Semiconductor Substrates And Associated Techniques App 20110186992 - Wu; Albert ; et al.	2011-08-04
Techniques And Configurations For Recessed Semiconductor Substrates App 20110186960 - Wu; Albert ; et al.	2011-08-04
Recessed Semiconductor Substrates App 20110186998 - Wu; Albert ; et al.	2011-08-04
Method Of Stacking Flip-chip On Wire-bonded Chip App 20110180913 - Liou; Shiann-Ming ; et al.	2011-07-28
Package Assembly Having A Semiconductor Substrate App 20110175218 - Liou; Shiann-Ming ; et al.	2011-07-21
Attaching Passive Components To A Semiconductor Package App 20110169163 - Liou; Shiann-Ming ; et al.	2011-07-14
Die-to-die wire-bonding Grant 7,969,022 - Liu , et al. June 28, 2	2011-06-28
Thermal solution for drive systems such as hard disk drives and digital versatile discs Grant 7,957,094 - Liu , et al. June 7, 2	2011-06-07
Embedded Chip Packages App 20110121444 - Wu; Albert ; et al.	2011-05-26
Semiconductor packaging with internal wiring bus Grant 7,911,053 - Liu , et al. March 22, 2	2011-03-22
Interconnect Layouts For Electronic Assemblies App 20110049710 - Kao; Huahung ; et al.	2011-03-03
Method of fabricating a device with ESD and I/O protection Grant 7,883,947 - Cheng , et al. February 8, 2	2011-02-08
Die Exposed Chip Package App 20100283143 - Liu; Chenglin ; et al.	2010-11-11
Integrated circuit devices with ESD and I/O protection Grant 7,808,075 - Cheng , et al. October 5, 2	2010-10-05
Thermal solution for drive systems such as hard disk drives and digital versatile discs Grant 7,764,462 - Liu , et al. July 27, 2	2010-07-27
Pillar structure on bump pad Grant 7,700,475 - Kao , et al. April 20, 2	2010-04-20
Thermal enhanced package Grant 7,675,157 - Liu , et al. March 9, 2	2010-03-09
Thermal Enhanced Package App 20090269891 - Liu; Chenglin ; et al.	2009-10-29
Drop-in heat sink and exposed die-back for molded flip die package Grant 7,560,309 - Kao , et al. July 14, 2	2009-07-14
Semiconductor Packaging With Internal Wiring Bus App 20080258291 - Liu; Chenglin ; et al.	2008-10-23
Chip On Leads App 20080128876 - Liu; Chenglin ; et al.	2008-06-05
Thermal enhanced package App 20070178622 - Liu; Chenglin ; et al.	2007-08-02
Semiconductor device power distribution system and method Grant 6,982,220 - Liou January 3, 2	2006-01-03
Semiconductor device power distribution system and method Grant 6,770,982 - Liou August 3, 2	2004-08-03
Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created Grant 5,650,667 - Liou July 22, 1	1997-07-22
Method and structure for forming vertical semiconductor interconnection Grant 5,057,907 - Ooi , et al. October 15, 1	1991-10-15