Ling; Zicheng Gary

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ling; Zicheng Gary.The latest application filed is for "testing vias and contacts in integrated circuit".

Company Profile

0.9.2

Ling; Zicheng Gary - San Jose CA
Ling; Zicheng Gary - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Testing vias and contracts in integrated circuit Grant 7,046,026 - Chao , et al. May 16, 2	2006-05-16
Method of generating an IC mask using a reduced database Grant 6,868,537 - Ho , et al. March 15, 2	2005-03-15
Testing vias and contacts in integrated circuit App 20040257105 - Chao, Tai-An ; et al.	2004-12-23
Testing vias and contacts in an integrated circuit Grant 6,784,685 - Chao , et al. August 31, 2	2004-08-31
Testing vias and contacts in integrated circuit fabrication App 20030025516 - Chao, Tai-An ; et al.	2003-02-06
Testing vias and contacts in integrated circuit fabrication Grant 6,503,765 - Chao , et al. January 7, 2	2003-01-07
Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers Grant 6,479,350 - Ling , et al. November 12, 2	2002-11-12
Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length Grant 6,306,702 - Hao , et al. October 23, 2	2001-10-23
Nitride disposable spacer to reduce mask count in CMOS transistor formation Grant 6,218,224 - Lukanc , et al. April 17, 2	2001-04-17
Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer Grant 6,153,455 - Ling , et al. November 28, 2	2000-11-28
Nitride disposable spacer to reduce mask count in CMOS transistor formation Grant 6,103,563 - Lukanc , et al. August 15, 2	2000-08-15

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