loadpatents
name:-0.0037548542022705
name:-0.0078811645507812
name:-0.0012860298156738
Ling; Zicheng G. Patent Filings

Ling; Zicheng G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ling; Zicheng G..The latest application filed is for "characterizing circuit performance by separating device and interconnect impact on signal delay".

Company Profile
1.7.3
  • Ling; Zicheng G. - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Determination of clock path delays and implementation of a circuit design
Grant 10,289,784 - Hwang , et al.
2019-05-14
Characterizing circuit performance by separating device and interconnect impact on signal delay
Grant 7,724,016 - Yuan , et al. May 25, 2
2010-05-25
Characterizing Circuit Performance By Separating Device And Interconnect Impact On Signal Delay
App 20090121737 - Yuan; Xiao-Jie ;   et al.
2009-05-14
Characterizing circuit performance by separating device and interconnect impact on signal delay
Grant 7,489,152 - Yuan , et al. February 10, 2
2009-02-10
Characterizing circuit performance by separating device and interconnect impact on signal delay
App 20060267618 - Yuan; Xiao-Jie ;   et al.
2006-11-30
Characterizing circuit performance by separating device and interconnect impact on signal delay
Grant 7,109,734 - Yuan , et al. September 19, 2
2006-09-19
Characterizing circuit performance by separating device and interconnect impact on signal delay
App 20050149777 - Yuan, Xiao-Jie ;   et al.
2005-07-07
Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits
Grant 6,867,580 - de Jong , et al. March 15, 2
2005-03-15
Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits
Grant 6,842,019 - de Jong , et al. January 11, 2
2005-01-11
Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits
Grant 6,727,710 - de Jong , et al. April 27, 2
2004-04-27

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