loadpatents
name:-0.0037569999694824
name:-0.014913082122803
name:-0.0011138916015625
Lindholm; Jeffrey V. Patent Filings

Lindholm; Jeffrey V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lindholm; Jeffrey V..The latest application filed is for "partial reconfiguration of a programmable logic device using an on-chip processor".

Company Profile
0.11.2
  • Lindholm; Jeffrey V. - Longmont CO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
Grant 8,001,511 - Bauer , et al. August 16, 2
2011-08-16
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
Grant 7,451,421 - Bauer , et al. November 11, 2
2008-11-11
Methods of routing programmable logic devices to minimize programming time
Grant 7,249,335 - Young , et al. July 24, 2
2007-07-24
Routing with frame awareness to minimize device programming time and test cost
Grant 7,149,997 - Young , et al. December 12, 2
2006-12-12
Methods of routing programmable logic devices to minimize programming time
Grant 7,143,384 - Young , et al. November 28, 2
2006-11-28
PLD device representation with factored repeatable tiles
Grant 7,107,565 - Lindholm , et al. September 12, 2
2006-09-12
Methods of generating test designs for testing specific routing resources in programmable logic devices
Grant 7,058,919 - Young , et al. June 6, 2
2006-06-06
Methods of resource optimization in programmable logic devices to reduce test time
Grant 6,944,809 - Lai , et al. September 13, 2
2005-09-13
Partial reconfiguration of a programmable logic device using an on-chip processor
Grant 6,907,595 - Curd , et al. June 14, 2
2005-06-14
Partial reconfiguration of a programmable logic device using an on-chip processor
App 20040113655 - Curd, Derek R. ;   et al.
2004-06-17
Clock template for configuring a programmable gate array
Grant 6,732,347 - Camilleri , et al. May 4, 2
2004-05-04
Methods of resource optimization in programmable logic devices to reduce test time
App 20040030975 - Lai, Andrew W. ;   et al.
2004-02-12
System and method for verifying configuration of a programmable logic device
Grant 6,553,523 - Lindholm , et al. April 22, 2
2003-04-22

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