Linde; Reed

Patent Applications and Registrations

Patent applications and USPTO patent grants for Linde; Reed.The latest application filed is for "system and method for binning at final test".

Company Profile

1.14.13

Linde; Reed - El Dorado Hills CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System And Method For Binning At Final Test App 20220184665 - Linde; Reed ; et al.	2022-06-16
System and method for binning at final test Grant 11,235,355 - Linde , et al. February 1, 2	2022-02-01
System And Method For Binning At Final Test App 20190160494 - Linde; Reed ; et al.	2019-05-30
System and method for binning at final test Grant 10,118,200 - Linde , et al. November 6, 2	2018-11-06
Systems and methods for test time outlier detection and correction in integrated circuit testing Grant 9,529,036 - Balog , et al. December 27, 2	2016-12-27
Correlation Between Manufacturing Segment And End- User Device Performance App 20160321594 - LINDE; Reed ; et al.	2016-11-03
Systems And Methods For Test Time Outlier Detection And Correction In Integrated Circuit Testing App 20150012237 - Balog; Gil ; et al.	2015-01-08
Systems and methods for test time outlier detection and correction in integrated circuit testing Grant 8,872,538 - Balog , et al. October 28, 2	2014-10-28
Misalignment indication decision system and method Grant 8,838,408 - Linde , et al. September 16, 2	2014-09-16
System and methods for parametric testing Grant 8,781,773 - Gurov , et al. July 15, 2	2014-07-15
Systems And Methods For Test Time Outlier Detection And Correction In Integrated Circuit Testing App 20130193994 - Balog; Gil ; et al.	2013-08-01
Systems and methods for test time outlier detection and correction in integrated circuit testing Grant 8,421,494 - Balog , et al. April 16, 2	2013-04-16
Misalignment Indication Decision System And Method App 20120123734 - LINDE; Reed ; et al.	2012-05-17
System And Methods For Parametric Testing App 20110251812 - GUROV; Leonid ; et al.	2011-10-13
Systems And Methods For Test Time Outlier Detection And Correction In Integrated Circuit Testing App 20110224938 - Balog; Gil ; et al.	2011-09-15
Systems and methods for test time outlier detection and correction in integrated circuit testing Grant 7,969,174 - Balog , et al. June 28, 2	2011-06-28
System And Method For Binning At Final Test App 20110000829 - Linde; Reed ; et al.	2011-01-06
Systems And Methods For Test Time Outlier Detection And Correction In Integrated Circuit Testing App 20090192754 - Balog; Gil ; et al.	2009-07-30
Methods for slow test time detection of an integrated circuit during parallel testing Grant 7,528,622 - Balog , et al. May 5, 2	2009-05-05
Datalog Management In Semiconductor Testing App 20090013218 - ROUSSEAU; Eran ; et al.	2009-01-08
Ultra low pin count interface for die testing Grant 7,405,586 - Gupta , et al. July 29, 2	2008-07-29
Ultra low pin count interface for die testing App 20070216438 - Gupta; Sunil ; et al.	2007-09-20
System and methods for test time outlier detection and correction in integrated circuit testing App 20070132477 - Balog; Gil ; et al.	2007-06-14

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